车用倒车雷达设计（基于51单片机）

The Verilog® Hardware Description Language (Verilog HDL) became an IEEE standard in 1995 as IEEEStd 1364-1995. It was designed to be simple, intuitive, and effective at multiple levels of abstraction in astandard textual format for a variety of design tools, including verification simulation, timiThe clear directive from the users for these three task forces was to start by solving some of the followingproblemsConsolidate existing IeeE Std 1364-1995Verilog generate statementMulti-dimensional arraysEnhanced Verilog file i/oRe-entrant tasksStandardize Verilog configurationsEnhance timing representationEnhance the vpi routinesAchievementsOver a period of four years the 1364 Verilog Standards Group(vsg) has produced five drafts of the lrmThe three task forces went through the EEe Std 1364-1995 lRM very thoroughly and in the process of consolidating the existing Lrm have been able to provide nearly three hundred clarifications and errata for theBehavioral, ASIC, and PLI sections. In addition, the vsg has also been able to agree on all the enhance-ments that were requested (including the ones stated above)Three new sections have been added. Clause 13, "Configuring the contents of a design, deals with configuration management and has been added to facilitate both the sharing of verilog designs between designersand/or design groups and the repeatability of the exact contents of a given simulation session Clause 15Timing checks, "has been broken out of Clause 17, "System tasks and functions, "and details more fullhow timing checks are used in specify blocks. Clause 16, "Backannotation using the Standard Delay Format(SDF), addresses using back annotation(IEEE Std 1497-1999)within IEEE Std 1364-2001Extreme care has been taken to enhance the vpi routines to handle all the enhancements in the behavioraland other areas of the lrm. minimum work has been done on the pli routines and most of the work hasbeen concentrated on the vpi routines. Some of the enhancements in the vpi are the save and restart simu-lation control, work area access, error handling, assign/deassign and support for array of instances, generateand file 1/0Work on this standard would not have been possible without funding from the cas society of the ieee andOpen verilog InternationalThe IEEE Std 1364-2001 Verilog standards Group organizationMany individuals from many different organizations participated directly or indirectly in the standardizationprocess. The main body of the Ieee Std 1364-2001 working group is located in the United States, with asubgroup in Japan (EIAJ/1364HDL)The members of the IEEE Std 1364-2001 working group had voting privileges and all motions had to beapproved by this group to be implemented the three task forces focused on their specific areas and theirrecommendations were eventually voted on by the Ieee Std 1364-2001 working group

这是关于MATLAB编程的免疫遗传算法，符合初学者，很好用的

【实例简介】max262的资料 自己画的板子 可编程滤波器

纯手工ViBe算法Demo，可以完整运行，很少使用循环计算，速度较快。适合调参数和修改算法使用，也可以直接用来检测现成的图像。有部分注释。

js 特效 html 特效 行走的小人js 特效 html 特效 行走的小人

空间插值算法的具体介绍， 很详细， 可以帮助对空间数据的掌握

这是一个java WEB小项目，用 Maven Springboot+mybatis+mysql+redis集成的小项目例子，可供新手进行参考学习，数据库是mysql 5.5 ,只是一个简单的小参考例子，测试过可以正常运行

所有开发人员或者技术团队，可以在本框架基础上做各种管理软件开发工作，里面所有相关业务代码都有Demo，大家可以学习着如何更好的使用UniGUI。如有技术上问题，可以下载另外一份《UniGUI集合说明--追月无名.doc》。

源码+原封数据集；本资源包括用各种机器学习方法（knn，决策树DecisionTree，随机森林，逻辑回归，支持向量机svm等）来对糖尿病进行预测的源码，包括数据集和导出的ipynb和py文件，对于新手学习和巩固机器学习算法有极大帮助。

nxp官方出的rc663、rc523、rd710驱动程序，包括标准的头文件、程序，能够直接使用