机柜VISIO图例

描述了各种PWM调制原理及在matlab的应用。

纯Matlab实现的复杂网络，网络生成，网络参数统计代码

基于opencv的轮廓和园检测，可以由于圆形目标的检测

使用OpenCV3.0进行双目三维重建。代码是用VS2013写的，OpenCV版本为3.0且包含扩展部分，如果不使用SIFT特征，可以修改源代码，然后使用官方未包含扩展部分的库。软件运行后会将三维重建的结果写入Viewer目录下的structure.yml文件中，在Viewer目录下有一个SfMViewer程序，直接运行即可读取yml文件并显示三维结构。

参数估计function [mu, sigma] = Bayesian_parameter_est(train_patterns, train_targets, sigma)

海思提供的媒体处理软件平台(Media Process Platform,简称MPP)，可支持应用软件快速开发。该平台对应用软件屏蔽了芯片相关的复杂的底层处理，并对应用软件直接提供MPI（MPP Program Interface）接口完成相应功能。该平台支持应用软件快速开发以下功能：输入视频捕获、H.265/H.264/JPEG 编码、H.265/H.264/JPEG 解码、视频输出显示、视频图像前处理（包括去噪、增强、锐化）、图像拼接、图像几何矫正、智能、音频捕获及输出、音频编解码等功能。HiMPP V4.0媒体处理软件开发参考目录目录前言……海思专有和保密信息文档版本00B08(2018-01-10)版权所有◎深圳市海思半导体有限公司HiMPP V4.0媒体处理软件开发参考前言前言概述本文为使用IMP媒体处理芯片进行开发的程序员而写,目的是供您在开发过程中查阅媒体处理软件开发包的冬和参考信息,包括APⅠ、头文件、错误码等。本文档描述 HIMPP媒体处理软件的各个API的使用方法,以及相关的数据结构和错误码」说明未有特殊说明,Hi359V100与Hi3559AV100内容一致。产品版本与本文档相对应的产品版本如下。产品名称产品版本操作系统Hi3559AV100ESLinux/huawei lilesHi3559AV100Linux/huawei litesHi35590V100Linux/huawei LitcOs读者对象本文档主要适用于以下工程师技术支持工程师软件开发工程师海思专有和保密信息文档版本00B08(2018-01-10)版权所有◎深圳市海思半导体有限公司HiMPP V4.0媒体处理软件开发参考前言约定符号约定在本文中可能出现下列标志,它们所代表的含义如下。符号说明表小有高度潜在危险,如果不能避免,会导致人员死亡或危险严重伤害表示有中度或低度潜在危险,如果不能避免,可能导致人警告员轻微或中等伤害。△表示有潜在风险,如果忽视这些文本,可能导致设备损坏、注意数据丢失、设备性能降低或不可预知的结果。@窍门表示能帮助您解决某个问题或节省您的时间。口说明表示是正文的附加信息,是对正文的强调和补充。通用格式约定格式说明宋体正文采用宋体表示黑体级、二级、三级标题采用黑体楷体警告、提小等内容一律用楷体,并且在内容前后増加线条与正文隔离。Termina1 Display”格式|“ Termina1 Display”格式表示屏幕输出信息。此外,屏幕输出信息中夹杂的用户从终端输入的信息采用加粗字体表示用双引号衣示文件路径。如“C: Program Files Huawei”。命令行格式约定格式意义粗体命令行关键字(命令中保持不变、必须照输的部分)采用加粗字体表示。海思专有和保密信息文档版本00B08(2018-01-10)版权所有◎深圳市海思半导体有限公司HiMPP V4.0媒体处理软件开发参考前言格式意义斜体命令行参数(命令中必须由实际值进行替代的部分)采用斜体表示表小用“[]”括起来的部分在命令配置时是可选的。XY衣示从两个或多个选项中选取…个[x|y|….表示从两个或多个选项中选取一个或者不选。x|y|….}*表示从两个或多个选项中选取多个,最少选取一个,最多选取所有选项。[x|y|…]衣示从两个或多个选项中选取多个或者不选修订记录修订记录累积了每次文档更新的说明。最新版本的文档包含以前所有文档版本的更新内谷。修订日期版本修订说明201801-1000B08第8次临时版本发布第2章系统控制23小节, HI MPI SYS MmapCache【注意】涉及修改;朋除HI MPI SYS Sctrcg和 HI MPI SYS〔 trEg’新增HI MPI SYS SetTuningConnect FH HI MPI SYS GetTuningConnect2.6.2和264涉及修改第3章视频输入33小节,图3-2和图3-4涉及修改,新增表3-334小节,新增 HI MPI VI SetDevAttrEx HI MPI VI TriggerFlash;HI MPIⅤ I SetPipe Crop、 HI MPI VI GetPipecrop、HI MPI VI Query Pipe Status, HI MPI VI EnablPipelnterruptHI MPI VI DisablPipelnterrupt / FW HI MPI VI QueryChnStatus删除 HI MPI VI GetDevFd35小节,删除 VI PIPE MAX WIDTH和Ⅴ I CHN MAX WIDTH;新增VI DEV ATTR EX S、 VI PIPE STATUS S、 VI FLASH MODE SVI FLASH ATTR S和 VI CHN STATUS S;Ⅴ I PIPE ATTR S和Ⅵ I CHN ATTR S【成员】涉及修改第4章视频输出4.1和42小节涉及修改4.3小节,新增HMPIⅴ o SetmodParam和 HI MPI VO GetModParam432小节, HI MPI VO Set VideoLayerPartitionMode和海思专有和保密信息文档版本00B08(2018-01-10)版权所有◎深圳市海思半导体有限公司HiMPP V4.0媒体处理软件开发参考前言修订日期版本修订说明HI MPI VO Get VideolaverPartition Mode涉及修改44小节, VO MAX CHN NUM【定义】和【芯片差异】涉及修改VO VIDEO LAYER ATTR S【差异说明】涉及修改;新增VO MOD PARAM S第5章视频处理子系统523小节涉及修改5.3小节,新增 HI MPI VPSS Sct GrpNRXParam和HI MPI VPSS GetGrpNRXParam54小节, VPSS MAX IMAGE WIDTHVPSS EXTCHN MAX IMAGE WIDTH、 VPSS GRP ATTR S、VPSS CHN ATTR S和 VPSS EXT CHN ATTR S涉及修改新增Ⅴ PSS GRP NRX PARAM S、 VPSS IP NUM和VPSS MODULE PARAMS S第6章视频编码623和6216涉及修改63小节,新增 HI MPI VENC Attach vbpool和 HI MPI VENC Detach VbPool64小节, VENC CHN STATUS S和Ⅴ ENC MOD H265ES涉及修改;新增VENCⅠ NTRA REFRESH MODE E和 VENC PARAM MOD RC S第7章视频解码7.2小节涉及修改73小节,新增 HI MPi VDEC Setchnattr74小节, VDEC CHN ATTR S、 VDEC ATTR VIDEO S涉及修改第8章区域管理8.3小节,新增 HI MPI RGn BatchBegin和 HI MPI RGn BatchEnd;删除HI MPI RGN Set Attach Field FH HI MPI RGN Get AttachField84小节涉及修改第9章音频923小节,新增衣99941小节,新增 AO SYSCHN CHNID和 AIO ISTYPE E第10章视频图形子系统10.22小节涉及修改10.3小节,HMPIⅤ gs AddScaletask至HMPIⅤ Gs AddOsdTaskarray的【注意】涉及修改;新增 HI MPI VGS AddRolationtask10.4小节, VGS DRAW LINE S、Ⅴ GS ADD COVER S和VGS MODULE PARAMS S【成员】涉及修改;新增Ⅴ GS IP NUM第12章拼接12.1涉及修改12.3小节,新增 HI MPI AVS SetModParan和 HI MPI AVS SetModParam;表12-1涉及修改海思专有和保密信息文档版本00B08(2018-01-10)版权所有◎深圳市海思半导体有限公司HiMPP V4.0媒体处理软件开发参考前言修订日期版本修订说明12.4小节, AVS PROJECTION MODE E、 AVS GAIN MODE E、AS SPLIT ATTR S、 AVS GRP ATTR S和 AVS CUBE MAP ATTR S【注意事项】涉及修改;新增 AVS MOD PARAM S第13章Proc调试信息13.14、13.16、13.17、13.18和13.24小节涉及修改2017-111500B07第7次临时版本发布,添加H3559AV100的相关内容第2章系统控制23小节,删除 HI MPI SYS IOMmap, HI MPI VB CreatePoolHI MPI VB GetBlock和 HI MPIⅤ B GetSupplement∧ddr【参数】涉及修改第3章视频输入3.3小节涉及修改34小节,新增 MPI VI SetPipeRepeatMode和HI MPI VI GetPipeRepeat ModeI MPI VI SetMipiBindDev HI MPI VI GetMipiBindDevHI MPI VI GctPipc Cmp param、 HI MPI VI SetchnAttr【芯片差异】涉及修改3.5小节,新增 I PIPE MAX WIDTH、Ⅵ I CHN MAX WIDTH和VI PIPE REPEAT MODE E第5章视频处理子系统521和52.3小节涉及修改5.4小节, VPSS MAX IMAGE WIDTH~VPSS EXTCHN MAX IMAGE HEIGHT【定义】涉及修改;VPSS GRP ATTR S、 VPSS CHN ATTR S、Ⅴ PSS EXT CHN ATTR S和VPSS GRP SHARPEN AUTO ATTR S【成员】涉及修改第6章视频编码表6-1、表6-3、表6-4和表6-5涉及修改623和6.24小节涉及修改63小节,新增 HI MPI VENC SctScenc modc和 HI MPI VENC GctScenc Modc64小节,新增 VENC H264 AVBR S、 VENC H65 AVBR S、VENC PARAM H264 AVR S、 VENC PARAM H265 AVBR S和VENC SCENE MODE E第10章视频图形子系统10.22小节涉及修改10.3小节,HMPlⅤ gs AddScaletask【注意】涉及修改10.4小节, VGS DRAW LⅠNES、 VGS ADD COⅤERS【成员】涉及修改第11章几何畸变矫正子系统11.2小节涉及修改第12章全景拼接12.2和12.3小节涉及修改124小节, AVS LUT ACCURACY E、 AVS FOV S、海思专有和保密信息文档版本00B08(2018-01-10)版权所有◎深圳市海思半导体有限公司HiMPP V4.0媒体处理软件开发参考前言修订日期版本修订说明AS CUBE MAP ATTR S、 AVS GRP ATTR S【注意】涉及修改第13章Proc调试信息13.15小节涉及修改2017-092900806第6次临时版本发布第2章系统控制新增22.3小节23小节,新增 HI MPI SYS SeⅤ IVPSSMode和HI MPI SYS GetVIVPSSMode24.1小节,新增 DATA RATE F; FRAME RATE CTRI.S【成员】涉及修改FRAME FLAG E【定义】和【成员】涉及修改:删除 SNAP TYPE E和FRAME SUPPLEMENT INFO S2.42小节,新增Ⅵ VPSS MODE E和VIⅤ PSS MODE S24.3小节, VIDEO SUPPLEMENT S【定义】和【成员】涉及修改第3章视频输入34小节, HI MPI VI SetPipeFrame Source到 HI MPIⅤ I Release Pipeframe涉及修改,新增 HI MPI VI Setchnalign和HMPIⅥ GetchnAlignHI MPI VI SetDevTimingAttr HI MPI VI Destroy PipeHI MPI VI GetPipeFisheye Config、HMPIⅤ SetChn Rotation和HI MPIⅥ I SetchnldCattr【注意】涉及修改35小节,新增 VI PIPE ONLINE MAX WIDTH、VI PIPE OFFLINE MAX WIDTH VI PIPE PARALLEL MAX WIDTHVI CHN OFFLINE MAX WIDTH NH VI CHN PARALLEL MAX WIDTH修改Ⅵ CHN ONLINE MAX WIDTH和 VI PIPE FRAME SOURCE E,朋除 I PIPI MODE E36小节,表3-6涉及修改第4章视频输出41小节,衣4-1涉及更新。4.2小节,涉及更新。4.3.2小节,新增HMPIⅤ o Set videoplayer Priority至HI MPI VO Get VideoLaverPartitionMode, HI MPI VO BatchBegin EHI MPI VO Get VideoLayer Boundary4.3.3小节,新增 HI MPI VO SetChnParam至HI MPI VO GetChnDisplay position,新增H! MPI VO Refreshchn、HI MPI VO SctChn Boundary, HI MPI VO Gct Chn Boundary FHHI MPI VO Getchn Region luma44小节涉及修改第5章视频处理子系统53小节,新增HMPIⅤ PSS Enable Backup Frame至HI MPI VPSS GetChnAlign54小节,新增ⅴ PSS SHARPEN GAIN NUM至海思专有和保密信息文档版本00B08(2018-01-10)版权所有◎深圳市海思半导体有限公司HiMPP V4.0媒体处理软件开发参考前言修订日期版本修订说明VPSS YUV SHPLUMA NUM,Ⅴ PSS LOW DELAY INFO S至VPSS GRP SHARPEN ATTR S第6章视频编码63和6.4小节涉及修改第7章视频解码7.3小节,新增 HI MPI VDEC Setrotation和 HI MPI VDEC SetrotationHI MPI VDEC Releaseframe和 HI MPI VDEC ReleaseUserData【注意】涉及修改7.4小节, VDEC STREAM S和 VDEC MOD PARAM S涉及修改第8章区域管理821节,衣8-1涉及修改第11章几何畸变矫正子系统11.5小节, RECT S【注意事项】涉及修改第12章全景拼接12.4小节,新增 AVS SPLIT NUM、 AVS SPLIT PIPE NUM、AVS CUBE MAP SURFACE NUM、 AVS SPLIT ATTR S和AVS CUBE MAP ATTR S第13章Proc调试信息13.6、13.10、13.11、13.13、13.15、13.17和13.24的【调试信息】和【参数说明】均涉及修改2017072000805第5次临时版本发布第2章系统控制23小节,新增 HI MPI SYS IOMmapHI MPI SYS Mmap、 HI MPI SYS Setscale Coeflevel【注意】涉及修改242小节, SCALE RANGE E和 COEFF LEⅤELE【定义】涉及修改SCALE COEFF LEVEL S【成员】涉及修改2.43小节,新增 ISP CONFIG INFO S第3章视频输入3.3小节,修改“从模式”相关内容34小节,新增HMPIⅤ I SetStitch GrpAttr和 HI MPI VI GetStitch GrpAttrHI MPIⅥ I SendPiperaw【注意】涉及修改3.5小节,新增Ⅴ I MAX STITCH GRP NUM、Ⅴ I SHARPEN GAIN NUMⅥ I AUTO ISO STRENGTH NUM、Ⅴ I STITCH GRP ATTR、VI PIPE RAW SOURCE E FH VI RAW INFO SⅥ I BAS SCALE ATTR S【定义】和【注意事项】涉及修改Ⅵ I NR ATTR S和Ⅵ I PIPE ATTR S【注意事项】涉及修改第5章视频处理子系统521、52.3和53小节涉及修改海思专有和保密信息文档版本00B08(2018-01-10)版权所有◎深圳市海思半导体有限公司

使用KMeans算法与BOF 算法实现图像检索，Matlab编码

本书涵盖了非线性规划的主要内容，包括无约束优化、凸优化、拉格朗日乘子理论和算法、对偶理论和方法等，并包含了大量的实际应用案例 .本书从无约束优化问题入手，通过直观分析和严谨证明给出了无约束优化问题的最优性条件，并讨论了梯度法、牛顿法、共轭方向法等实用算法 .进而本书将无约束优化问题的最优性条件和算法推广到具有凸集约束的优化问题中，进一步讨论了处理约束问题的可行方向法、条件梯度法、梯度投影法、双矩阵投影法、坐标块下降法等算法 .拉格朗日乘子理论和算法是非线性规划的核心内容之一，也是本书的重点 .本书中的第 3、4章详尽地论述了这方面的内容 .本书首先从等式约束优化问题最优解的必要条件入手，给出了

微电子电路设计第五版,Richard C. Jaeger, Traveis N. Blalock编著。FIETH EDITIONMICROELECTRONICHM-M- CIRCUIT DESIGNRICHARD C. JAEGERAuburn UniversityTRAVIS N. BLALOCKUniversity of VirginiaMcGrawEducationGrawEducationMICROELECTRONIC CIRCUIT DESIGN. FIFTH EDITIOPublished by McGraw-Hill Education, 2 Penn Plaza, New York, NY 10121 CopyrightC 2016 by McGraw-Hill EducationAll rights reserved. Printed in the United States of America. Previous editions 2011, 2008, and 2004. No part of thispublication may be reproduced or distributed in any form or by any means, or stored in a database or retrieval system,without the prior written consent of McGraw-Hill Education, including, but not limited to, in any network or otherelectronic storage or transmission, or broadcast for distance learninSome ancillaries, including electronic and print components, may not be available to customers outside the United StatesThis book is printed on acid-free pape1234567890DOw/DOw1098765ISBN978-0-07-352960-8MHID0-07-352960-5sident Products markets Kurt LVice President, General Manager, Products Markets: Marty Langece President, Content Design Delivery: Kimberly Meriwether DavidManaging director: Thomas TimpGlobal Publisher Raghu srinivasanDirector. Prodrelopment: RoDirector, Digital Content Development: Thomas Scaife, Ph DProduct develoVincent brashMarketing manager: Nick Mc faddenDirector, Content Design Delivery: Linda avenariusProgram meSchillingContent Project Managers: Jane Mohr, Tammy Juran, and Sandra M. SchneeBuyer: Jennifer PickelDesign: Studio Montage, St Louis, MOContent Licensing Specialist: DeAnna DausenerCompositor: MPS LimitedPrinter.R. DonnellAll credits appearing on page or at the end of the book are considered to be an extension of the copyright pageLibrary of Congress Cataloging-in-Publication DataJaeger. Richard cMicroelectronic circuit design/Richard C. Jaeger, Auburn University,Travis N. Blalock, University of Virginia. --Fifth editionpages cmIncludes bibliographical references and indexISBN978-0-07-352960-8(alk. paper)-ISBN0-07-338045-8(alk. paper)d 1. Integrated circuits--Design and construction. 2. Semiconductors--Design and construction. 3. Electronic circuitesign. I. Blalock, Travis N. Il. TitleTK7874.J3332015621.3815-dc232014040020The Internet addresses listed in the text were accurate at the time of publication. The inclusion of a website does not indicatean endorsement by the authors or McGraw-Hill Education, and McGraw-Hill Education does not guarantee the accuracy ofthe information presented at these siteswww.mhhe.comTOTo Joan, my loving wife and life long partnerRichard C. JaegerIn memory of my father, Professor Theron vaughnBlalock, an inspiration to me and to the countlessstudents whom he mentored both in electronicdesign and in life.Travis n blalockBRIEF CONTENTSPreface xxChapter-by-Chapter Summary XXV12 Operational Amplifier Applications 685PART ONE13 Small-Signal Modeling and LinearSOLID-STATE ELECTRONICS AND DEVICESAmplification 77014 Single-Transistor Amplifiers 8411 Introduction to Electronics 32 Solid-State Electronics 4115 Differential Amplifiers and Operational Amplifier3 Solid-state Diodes and Diode circuits 72Design 9524 Field-Effect Transistors 14416 Analog Integrated Circuit Design Techniques 10315 Bipolar Junction Transistors 21517 Amplifier Frequency Response 111318 Transistor Feedback Amplifiers andPART TWOOscillators 1217DIGITAL ELECTRONICSAPPENDICES6 Introduction to Digital Electronics 2837 Complementary MOS (CMOS) Logic Design 359A Standard Discrete Component Values 12918 MOS Memory Circuits 414B Solid-State Device Models and sPIce simulationParameters 12949 Bipolar Logic Circuits 455C TWo-Port Review 1299PART THREIndex 1303ANALOG ELECTRONICS10 Analog Systems and Ideal OperationalAmplifiers 51711 Nonideal Operational Amplifiers and FeedbackAmplifier Stability 587CONTENTSPreface xxCHAPTER 2Chapter-by-Chapter Summary XXVSOLID-STATE ELECTRONICS 41PART ONE2.1 Solid-State Electronic materials 432.2 Covalent bond model 44SOLID-STATE ELECTRONICS2.3 Drift Currents and mobility inAND DEVICES 1Semiconductors 472.3.1 Drift Currents 47CHAPTER 12.3.2 Mobility 48INTRODUCTION TO ELECTRONICS 32.3.3 Velocity Saturation 482.4 Resistivity of Intrinsic Silicon 491.1 A Brief History of Electronics: From2.5 Impurities in Semiconductors 50Vacuum Tubes to Giga-Scale Integration 52.5.1 Donor Impurities in silicon 511.2 Classification of Electronic Signals 82.5.2 Acceptor Impurities in Silicon 511.2.1 Digital signals 92.6 Electron and hole concentrations in1.2.2 Analog Signals 9Doped semiconductors 511.2.3 A/D and D/A Converters--Bridging2.6.1Type Material (ND >NA)52the analog and Digital2.6.2 p-Type Material (N,A>ND)53Domains 102.7 Mobility and Resistivity in Doped1.3 Notational conventions 12Semiconductors 541.4 Problem-Solving Approach 132.8 Diffusion currents 581.5 Important Concepts from Circuit2. 9 Total Current 59Theory 152.10 Energy Band Model 601.5.1 Voltage and current Division 152.10.1 Electron-Hole pair generation in1.5.2 Thevenin and norton circuitan intrinsic semiconductor 60Representations 162.10.2 Energy Band Model for a Doped1.6 Frequency Spectrum of ElectronicSemiconductor 61Signals 212.10.3 Compensated semiconductors 611.7 Amplifiers 222.11 Overview of Integrated circuit1.7.1 Ideal operational amplifiers 23Fabrication 631.7.2 Amplifier Frequency Response 25Summary 661.8 Element Variations in Circuit Design 26Key Terms 671.8.1 Mathematical modeling ofReference 68Tolerances 26Additional Reading 681.8.2 Worst-Case Analysis 27Problems 688.3 Monte Carlo analysis 291.8.4 Temperature Coefficients 32CHAPTER 31.9 Numeric Precision 34SOLID-STATE DIODES AND DIODE CIRCUITS 72Summary 34Key Terms 353.1 The pn Junction Diode 73References 363.1.1 pn Junction Electrostatics 73Additional Reading 363.1.2 nternal diode currents 77Problems 363.2 The i-v Characteristics of the diode 78VIllContents3.3 The Diode Equation: A Mathematica3.15 Full-Wave Bridge Rectification 123Model for the diode 803.16 Rectifier Comparison and Design3.4 Diode Characteristics under reverse, ZeroTradeoffs 124and forward bias 833.17 Dynamic Switching Behavior of the Diode 1283.4.1 Reverse bias 833.18 Photo diodes, solar cells, and3. 4.2 Zero bias 83Light-Emitting Diodes 1293.4.3 Forward Bias 843.18.1 Photo diodes and3.5 Diode Temperature Coefficient 86Photodetectors 1293.6 Diodes under reverse bias 863.18.2 Power Generation from Solar Cells 1303.6.1 Saturation Current in real3.18. 3 Light-Emitting Diodes(LEDs)13Diodes 87Summary 1323.6.2 Reverse Breakdown 89Key Terms 1333.6.3 Diode model for the breakdownReference 134Region 90Additional Reading 1343.7 pn Junction Capacitance 90Problems 1343.7.1 Reverse bias 903.7.2 Forward Bias 91CHAPTER 43.8 Schottky Barrier Diode 933.9 Diode SPICE Model and layout 93FIELD-EFFECT TRANSISTORS 1443.9.1 Diode Layout 944.1 Characteristics of the MOS Capacitor 1453.10 Diode Circuit Analysis 954.1.1 Accumulation Region 1463.10.1 Load-Line Analysis 964.1.2 Depletion Region 1473.10.2 Analysis Using the Mathematical4.1.3 Inversion Region 147Model for the diode 974.2 The nmos transistor 1473.10.3 The Ideal diode model 1014.2.1 Qualitative i-v Behavior of the3.10.4 Constant Voltage Drop Model 103NMOS Transistor 1483.10.5 Model Comparison and4.2.2 Triode Region Characteristics ofDiscussion 104the nmos transistor 1493.11 Multiple-Diode Circuits 1054.2.3 On Resistance 1523.12 Analysis of Diodes Operating in the4.2.4 Transconductance 153Breakdown Region 1084.2.5 Saturation of the i-v3.12.1 Load-Line Analysis 108Characteristics 1543.12.2 Analysis with the Piecewise4.2.6 Mathematical model in theLinear model 108Saturation (Pinch-off)3.12.3 Voltage regulation 109Region 1553.12.4 Analysis Including Zener4.2.7 Transconductance in saturation 156Resistance 1104.2.8 Channel-Length Modulation 1563.12.5 Line and Load Regulation 1114.2.9 Transfer characteristics and3.13 Half-Wave Rectifier Circuits 112Depletion-Mode MosFETs 1573.13.1 Half-Wave Rectifier with resistor4.2.10 Body Effect or SubstrateLoad 112Sensitivity 1593.13.2 Rectifier Filter Capacitor 1134.3 PMOS Transistors 1603.13.3 Half-Wave Rectifier with rc load 1144.4 MOSFET Circuit Symbols 1623. 13.4 Ripple Voltage and Conduction4.5 Capacitances in MOS Transistors 165Interval 1154.5.1 NMOs Transistor Capacitances in3.13.5 Diode Current 117the Triode region 1653.13.6 Surge Current 1194.5.2 Capacitances in the Saturation3.13.7 Peak-Inverse-Voltage(PlV)Rating 119Region 1663.13.8 Diode Power Dissipation 1194.5.3 Capacitances in Cutoff 1663.13.9 Half-Wave Rectifier with Negative4.6 MOSFET Modeling in SPICE 167Output Voltage 1204.7 MOS Transistor Scaling 1683.14 Full-Wave Rectifier Circuits 1224.7.1 Drain Current 1693. 14.1 Full-Wave Rectifier with Negative4.7.2 Gate Capacitance 169Output Voltage 1234.7.3 Circuit and power densities 169ContentsIX4.7.4 Power-Delay Product 1705.3 The pnp Transistor 2234.7.5 Cutoff Frequency 1705.4 Equivalent Circuit Representations for the4.7.6 High Field Limitations 171Transport Models 2254.7.7 The unified mos transistor model5.5 The i-v Characteristics of the bipolarIncluding High Field Limitations 172Transistor 2264.7.8 Subthreshold conduction 1735.5.1 Output Characteristics 2264.8 MOs Transistor Fabrication and layout5.5.2 Transfer characteristics 227Design Rules 1745.6 The Operating Regions of the Bipolar4.8.1 Minimum Feature size andTransistor 227Alignment Tolerance 1745.7 Transport Model Simplifications 2284.8.2 Mos Transistor Layout 1745.7.1 Simplified Model for the Cutoff4.9 Biasing the NMOS Field-EffectRegion 229Transistor 1785.7.2 Model Simplifications for the4.9.1 Why Do We Need Bias? 178Forward-Active Region 2314.9.2 Four-Resistor Biasing 1805.7.3 Diodes in Bipolar Integrated4.9.3 Constant Gate-Source VoltageCircuits 237Bias 1845.7.4 Simplified Model for the4.9.4 Graphical analysis for theReverse-Active Region 238Q-Point 1845.7.5 Modeling Operation in the4.9.5 Analysis Including Body Effect 184Saturation Region 2404.9.6 Analysis Using the Unified5.8 Nonideal Behavior of the bipolarModel 187Transistor 2434.10 Biasing the PMos Field-Effect Transistor 1885.8.1 Junction Breakdown Voltages 2444.11 The junction Field-Effect Transistor5.8.2 Minority-Carrier Transport in theUFET190Base Region 2444.11.1 The JFET With Bias Applied 195.8.3 Base Transit time 2454.11.2 JFET Channel with Drain-Source5.8.4 Diffusion Capacitance 247Bias 1935.8.5 Frequency Dependence of the4.11.3 n-Channel jfet i-v Characteristics 193Common-Emitter current gain 2484.11.4 The p-Channel JFET 1955.8.6 The Early Effect and Early4.11.5 Circuit Symbols and JFET ModelVoltage 248Summary 1955.8.7 Modeling the Early Effect 2494.11.6 JFET Capacitances 1965.8.8 Origin of the Early Effect 2494.12 JFET Modeling in Spice 1965.9 Transconductance 2504.13 Biasing the JFET and Depletion-Mode5.10 Bipolar Technology and sPiCe Model 251MOSFET 1975.10.1 Qualitative Description 251Summary 2005.10.2 SPICE Model Equations 252Key Terms 2025.10.3 High-Performance BipolarReferences 202Transistors 253Problems 2035.11 Practical bias circuits for the bjt 2545.11.1 Four-Resistor bias network 256CHAPTER 55.11.2 Design Objectives for theBIPOLAR JUNCTION TRANSISTORS 215Four-Resistor bias network 2585.11.3 terative Analysis of the5.1 Physical Structure of the BipolarFour-Resistor bias circuit 262Transistor 2165.12 Tolerances in bias circuits 2625.2 The Transport Model for the npn5. 12.1 Worst-Case Analysis 263Transistor 2175. 12.2 Monte Carlo Analysis 2655.2.1 Forward Characteristics 218Summary 2685.2.2 Reverse Characteristics 220Key Terms 2705.2.3 The Complete Transport ModelReferences 270Equations for Arbitrary BiasProblems 271Conditions 221

一.dwmain.m为定位程序，1.调用了gj.m（轨迹方程）2.SC.m（时差定位程序）3.pc.m（频差定位程序） 二.GDOP_main.m为时差定位GDOP图 三.pcgdop_main.m为频差定位GDOP图 【程序说明】 一.dwmain.m为定位程序，1.调用了gj.m（轨迹方程）2.SC.m（时差定位程序）3.pc.m（频差定位程序）二.GDOP_main.m为时差定位GDOP图三.pcgdop_main.m为频差定位GDOP图