多径信道下 简单OFDM matlab仿真

三、 设计要求A、电路能输出正弦波、方波和三角波等三种波形；B、输出信号的频率要求可调；C、拟定测试方案和设计步骤；D、根据性能指标，计算元件参数，选好元件，设计电路并画出电路图；E、在面包板上或万能板上安装电路；F、测量输出信号的幅度和频率；H、写出设计性性报告。

实现了ECC点乘，二进制伽罗瓦域，顶层点乘算法模块使用了一篇论文中介绍的高速点乘运算

运用生长法实现DTIN的生成，先生成随机点，然后采用三角形生长算法形成三角形。采用动态数组，所以在三角网产生之后也能将后来产生的点加入到新的三角网之中。

The Verilog® Hardware Description Language (Verilog HDL) became an IEEE standard in 1995 as IEEEStd 1364-1995. It was designed to be simple, intuitive, and effective at multiple levels of abstraction in astandard textual format for a variety of design tools, including verification simulation, timiThe clear directive from the users for these three task forces was to start by solving some of the followingproblemsConsolidate existing IeeE Std 1364-1995Verilog generate statementMulti-dimensional arraysEnhanced Verilog file i/oRe-entrant tasksStandardize Verilog configurationsEnhance timing representationEnhance the vpi routinesAchievementsOver a period of four years the 1364 Verilog Standards Group(vsg) has produced five drafts of the lrmThe three task forces went through the EEe Std 1364-1995 lRM very thoroughly and in the process of consolidating the existing Lrm have been able to provide nearly three hundred clarifications and errata for theBehavioral, ASIC, and PLI sections. In addition, the vsg has also been able to agree on all the enhance-ments that were requested (including the ones stated above)Three new sections have been added. Clause 13, "Configuring the contents of a design, deals with configuration management and has been added to facilitate both the sharing of verilog designs between designersand/or design groups and the repeatability of the exact contents of a given simulation session Clause 15Timing checks, "has been broken out of Clause 17, "System tasks and functions, "and details more fullhow timing checks are used in specify blocks. Clause 16, "Backannotation using the Standard Delay Format(SDF), addresses using back annotation(IEEE Std 1497-1999)within IEEE Std 1364-2001Extreme care has been taken to enhance the vpi routines to handle all the enhancements in the behavioraland other areas of the lrm. minimum work has been done on the pli routines and most of the work hasbeen concentrated on the vpi routines. Some of the enhancements in the vpi are the save and restart simu-lation control, work area access, error handling, assign/deassign and support for array of instances, generateand file 1/0Work on this standard would not have been possible without funding from the cas society of the ieee andOpen verilog InternationalThe IEEE Std 1364-2001 Verilog standards Group organizationMany individuals from many different organizations participated directly or indirectly in the standardizationprocess. The main body of the Ieee Std 1364-2001 working group is located in the United States, with asubgroup in Japan (EIAJ/1364HDL)The members of the IEEE Std 1364-2001 working group had voting privileges and all motions had to beapproved by this group to be implemented the three task forces focused on their specific areas and theirrecommendations were eventually voted on by the Ieee Std 1364-2001 working group

【实例简介】

应用Visual+C++平台的GPS精密单点定位程序设计

常规波束形成 的matlab代码，包含均匀线阵方向图、 波束宽度与波达方向及阵元数的关系、以及阵元间距对旁瓣的影响等内容，代码可以直接拷贝到matlab环境下执行，也有注释

现代电力系统分析 电力系统分析（上，下册）电力系统稳态分析

这个matlab程序实现了目标对象的图像分割与提取技术，附件里的程序以车牌的检测与识别为例，效果非常好。

目前关于蜂群算法的文献较少,故不仅是拓宽蜂群算法应用范围的有效尝试,同时也给带时间窗车辆路径问题提供了一种新的解决方法。