官网下载完整的Ant，包括Ant-contrib

本源码包采用的是STM32F103C8T6，可以替换为你想要的STM32其他芯片，移植请参考我的博客文档http://blog.csdn.net/cumtwys/article/details/7178096

很好的配电网重构程序，已经调试通过，很适合初学者。

The Verilog® Hardware Description Language (Verilog HDL) became an IEEE standard in 1995 as IEEEStd 1364-1995. It was designed to be simple, intuitive, and effective at multiple levels of abstraction in astandard textual format for a variety of design tools, including verification simulation, timiThe clear directive from the users for these three task forces was to start by solving some of the followingproblemsConsolidate existing IeeE Std 1364-1995Verilog generate statementMulti-dimensional arraysEnhanced Verilog file i/oRe-entrant tasksStandardize Verilog configurationsEnhance timing representationEnhance the vpi routinesAchievementsOver a period of four years the 1364 Verilog Standards Group(vsg) has produced five drafts of the lrmThe three task forces went through the EEe Std 1364-1995 lRM very thoroughly and in the process of consolidating the existing Lrm have been able to provide nearly three hundred clarifications and errata for theBehavioral, ASIC, and PLI sections. In addition, the vsg has also been able to agree on all the enhance-ments that were requested (including the ones stated above)Three new sections have been added. Clause 13, "Configuring the contents of a design, deals with configuration management and has been added to facilitate both the sharing of verilog designs between designersand/or design groups and the repeatability of the exact contents of a given simulation session Clause 15Timing checks, "has been broken out of Clause 17, "System tasks and functions, "and details more fullhow timing checks are used in specify blocks. Clause 16, "Backannotation using the Standard Delay Format(SDF), addresses using back annotation(IEEE Std 1497-1999)within IEEE Std 1364-2001Extreme care has been taken to enhance the vpi routines to handle all the enhancements in the behavioraland other areas of the lrm. minimum work has been done on the pli routines and most of the work hasbeen concentrated on the vpi routines. Some of the enhancements in the vpi are the save and restart simu-lation control, work area access, error handling, assign/deassign and support for array of instances, generateand file 1/0Work on this standard would not have been possible without funding from the cas society of the ieee andOpen verilog InternationalThe IEEE Std 1364-2001 Verilog standards Group organizationMany individuals from many different organizations participated directly or indirectly in the standardizationprocess. The main body of the Ieee Std 1364-2001 working group is located in the United States, with asubgroup in Japan (EIAJ/1364HDL)The members of the IEEE Std 1364-2001 working group had voting privileges and all motions had to beapproved by this group to be implemented the three task forces focused on their specific areas and theirrecommendations were eventually voted on by the Ieee Std 1364-2001 working group

1、《手把手教你学DSP》配套的手册；2、《手把手教你学DSP》配套的例程；3、《手把手教你学DSP》配套的编程素材；4、《手把手教你学DSP》高清电子书，带索引；

用WinHex软件打开台达PLC程序（DVP格式），修改并保存破解了程序和项目密码。

利用多尺度高斯函数去除场景的光照分量；然后构造了一种二维伽马函数，利用光照分量的分布特性调整二维伽马函数的参数，降低光照过强区域的亮度值，提高光照过暗区域的亮度值，最终实现对光照不均匀图像的自适应校正处理。

基于labview的音乐播放器，有暂停、调节音量、进度条、伪旋律图等，不过受控件限制，只能播放wav格式文件

基于MATLAB的QPSK在瑞利、高斯和莱斯信道下仿真

心电信号 QRS MATLAB，心电信号的波形检测以及基于神经网络的分类

径向基函数（Radial Basis Functions，以下简称RBF）在数值和科学计算等领域被广泛应用，例如解微分方程、人工神经网络、曲面重建、计算机辅助设计、计算机图形学和多元插值等。RBF 插值方法不受输入参数的限制，可以进行高维插值。