MAX485两单片机半双工通信（含程序和电路图）

在winform 中画流程图,用户拖动控件时，线条跟着变

实现了快速相机标定，方法是利用了RAC标定

基于stm32的hmc5983和mpu6500的驱动程序，支持iic和spi通讯，另外可与山外上位机连接，显示波形。

适用于电力系统仿真的实际需要，ieee19机39节电系统

SAP（System, Applications, and Products in Data Processing）公司是全球最大的管理软件供应商，其主打产品R/3系统是ERP产品的领导者，涵盖了企业管理业务的各个方面，ABAP （Advanced Business Application Programming）是SAP/R3系统的开发工具，是第四代支持结构化程序设计的语言。　　本书把相当复杂的SAP技术以非常简单的方式表达，非常直接地描述SAP技术，并采用大量的图片资料，使读者能清晰地了解SAP技术。本书主要介绍了：ABAP所需的开发环境，ABAP开发的主要内容，开发事务代码汇总索引；A

教务管理系统（c#）完整代码+数据库教务管理系统（c#）完整代码+数据库教务管理系统（c#）完整代码+数据库

fpga开发，峰值采样计数，verilog代码

The Verilog® Hardware Description Language (Verilog HDL) became an IEEE standard in 1995 as IEEEStd 1364-1995. It was designed to be simple, intuitive, and effective at multiple levels of abstraction in astandard textual format for a variety of design tools, including verification simulation, timiThe clear directive from the users for these three task forces was to start by solving some of the followingproblemsConsolidate existing IeeE Std 1364-1995Verilog generate statementMulti-dimensional arraysEnhanced Verilog file i/oRe-entrant tasksStandardize Verilog configurationsEnhance timing representationEnhance the vpi routinesAchievementsOver a period of four years the 1364 Verilog Standards Group(vsg) has produced five drafts of the lrmThe three task forces went through the EEe Std 1364-1995 lRM very thoroughly and in the process of consolidating the existing Lrm have been able to provide nearly three hundred clarifications and errata for theBehavioral, ASIC, and PLI sections. In addition, the vsg has also been able to agree on all the enhance-ments that were requested (including the ones stated above)Three new sections have been added. Clause 13, "Configuring the contents of a design, deals with configuration management and has been added to facilitate both the sharing of verilog designs between designersand/or design groups and the repeatability of the exact contents of a given simulation session Clause 15Timing checks, "has been broken out of Clause 17, "System tasks and functions, "and details more fullhow timing checks are used in specify blocks. Clause 16, "Backannotation using the Standard Delay Format(SDF), addresses using back annotation(IEEE Std 1497-1999)within IEEE Std 1364-2001Extreme care has been taken to enhance the vpi routines to handle all the enhancements in the behavioraland other areas of the lrm. minimum work has been done on the pli routines and most of the work hasbeen concentrated on the vpi routines. Some of the enhancements in the vpi are the save and restart simu-lation control, work area access, error handling, assign/deassign and support for array of instances, generateand file 1/0Work on this standard would not have been possible without funding from the cas society of the ieee andOpen verilog InternationalThe IEEE Std 1364-2001 Verilog standards Group organizationMany individuals from many different organizations participated directly or indirectly in the standardizationprocess. The main body of the Ieee Std 1364-2001 working group is located in the United States, with asubgroup in Japan (EIAJ/1364HDL)The members of the IEEE Std 1364-2001 working group had voting privileges and all motions had to beapproved by this group to be implemented the three task forces focused on their specific areas and theirrecommendations were eventually voted on by the Ieee Std 1364-2001 working group

工资管理系统1、系统功能的基本要求： 员工每个工种基本工资的设定 加班津贴管理，根据加班时间和类型给予不同的加班津贴； 按照不同工种的基本工资情况、员工的考勤情况产生员工的每月的月工资； 员工年终奖金的生成，员工的年终奖金计算公式＝（员工本年度的工资总和＋津贴的总和）/12； 企业工资报表。能够查询单个员工的工资情况、每个部门的工资情况、按月的工资统计，并能够打印；2、数据库要求：在数据库中至少应该包含下列数据表： 员工考勤情况表； 员工工种情况表，反映员工的工种、等级，基本工资等信息； 员工津贴信息表，反映员工的加班时间，加班类别、加班天数、津贴情况等；

滤波器是一种选频装置，可以使信号中特定的频率成分通过，而极大地衰减其它频率成分。在测试装置中，利用滤波器的这种选频作用，可以滤除干扰噪声或进行频谱分析。广义地讲，任何一种信息传输的通道（媒质）都可视为是一种滤波器。因为，任何装置的响应特性都是激励频率的函数，都可用频域函数描述其传输特性。因此，构成测试系统的任何一个环节，诸如机械系统、电气网络、仪器仪表甚至连接导线等等，都将在一定频率范围内，按其频域特性，对所通过的信号进行变换与处理。本文所述内容属于模拟滤波范围。主要介绍模拟滤波器原理、种类、数学模型、主要参数、ＲＣ滤波器设计。尽管数字滤波技术已得到广泛应用，但模拟滤波在自动检测、自动控制