MATLAB 优化问题 26个测试函数

TIN triangle delaunay 构造三角网的经典算法，是由乔纳森教授编写的原创算法，

Fluent 中文UDF很好的学习课件，如果您对FLUENT感兴趣，我们可以经常沟通，祝大家好运

本毕设使用stm32作为主控芯片，dht11为温湿度传感器，MQ-2获取有害气体浓度，LCD5110作为显示；sim900a作为短信发送；Android手机自动接收短信。此压缩包包括：stm32程序，Android程序，PCB图，毕设论文

此程序，是OQPSK的仿真程序，包括，正交调制的输出波形，功率谱分析，及误码率分析，解调采用正交解调方式

使用CC2591作为CC2530的功放, CC2591 PAThe absolute maximum ratings and operating conditions listed in the CC2530 datasheet [1]and the CC2591 datasheet [4] must be followed at all times. Stress exceeding one or more ofthese limiting values may cause permanent damage to any of the devicesNote that these characteristics are only valid when using the recommended register settingspresented in Section 4.6 and in Chapter 8, and the CC2530 - EM reference designOperating Frequency240524835MHzOperating Supply Voltage2036VOperating Temperature-40CTC=25C, VDD=3.0V, f=2440 MHz if nothing else is stated. All parameters are measuredon the CC2530-Cc2591EM reference design [11] with a 50 Q2 loadReceive CurrentWait for sync, -90 dBm input levelWait for sync, -50 dBm input level24mATXPOWER OXE5166mATXPOWER OXD5149mATXPOWER OXC5138mATXPOWER OXB5127mATransmit currentTXPOWER OXA5115ATXPOWER = 0X95100mATXPOWER = 0X8594ATXPOWE=0×75mATXPOWE=0×6579APower Down Current PM2UAISTRUMENTSPage 3 of 19SWRA308ATC=25C, Vdd=3.0V, f= 2440 MHz if nothing else is stated. All parameters are measuredon the CC2530-CC2591 EM reference design with a 50 Q2 loadReceive Sensitivity HGM 1 %PER, IEEE 802. 15.4[6] requires -85 dBm-988dBmReceive Sensitivity LGM1 PER, IEEE 802. 15.4 [6] requires -85 dBm-90.4dBmSaturationlEEE 802.15. 4 [6] requires-20 dBm10dBmWanted signal 3 db above the sensitivity levelIEEE 802.15.4 modulated interferer at ieee 802.15.4 channelsInterferer Rejection+5 MHz from wanted signal, IEEE 802. 15. 4 [6] requires 0 dBdB+10 MHz from wanted signal, IEEE 802. 15. 4 [6] requires 30 dB49dB+20 MHz from wanted signal wanted signal at- 82d BmdBdue to in the external lna and the offset in cc2530 the rssi readouts from cc2530CC2591 is different from rssi offset values for a standalone cc2530 design the offsetvalues are shown in table 4.4High Gain Mode79LoW Gain mode67Real rssi Register value-Rssl offsetISTRUMENTSPage 4 of 19SWRA308ATc=25C, Vdd=3.0V, f=2440 MHz if nothing else is stated All parameters are measuredon the CC2530-CC2591 EM reference design with a 50 Q2 load Radiated measurements aredone with the kit antennaRadiated Emissionwith TXPOWer Oxe5Conducted 2. RF (FCC restricted band)-462|dBmConducted 3. RF(FCC restricted band46.5 dBmComplies withFCC 15.247. SeeChapter 7 for moredetails about regulatoryRadiated 2.RF(FCC restricted band)42.2dBmrequirements andcomplianceIEEE 802.15.4[6]requires max.35%%Measured as defined by IEEE 802.15. 4 6TXPOWER OxE5. f= EEE 802.15. 4 channels13TXPOWER= OXD5. f= EEE 802.15.4 channelsTXPOWER= OXC5 f= EEE 802.15.4 channelsMax error∨ ectorTXPOWER OxB5 f= IEEE 802.15. 4 channelsMagnitude(EVM)TXPOWER OxA5. f= IEEE 802.15.4 channelsTXPOWER 0X95. f= IEEE 802. 15.4 channels643333%%%%%%%TXPOWER= 0x85. f= iEEE 802. 15.4 channelsTXPOWER =0x75 f= IEEE 802. 15.4 channels%TXPOWER= 065. f= iEEE 802. 15.4 channelsThe RF output power of the CC2530- CC2591 EM is controlled by the 7-bit value in theCC2530 TXPOWER register. Table 4.6 shows the typical output power and currentconsumption for the recommended power settings The results are given for Tc= 25 C, Vdd3.0V and f= 2440 MHz, and are measured on the cC2530-CC2591 EM reference designwith a 50 Q2 load. For recommendations for the remaining CC2530 registers, see Chapter 8 oruse the settings given by SmartRF StudioOXE520166OxD519149OxC18138OxB517127OxA5161150x95141000x8513940X75860x651079Note that the recommended power settings given in Table 4.6 are a subset of all the possibleTXPOWER register settings. However, using other settings than those recommended mightINSTRUMENTSPage 5 of 19SWRA308Aresult in suboptimal performance in areas like current consumption, EVM, and spuriousemissionTc=25C, Vdd=3.0V, f=2440 MHz if nothing else is stated All parameters are measuredon the CC2530-CC2591EM reference design with a 50 32 load2221-2V201918171611121314151617181920212223242526251510OxE5OxC5OxA50X850x65540-30-20-1001020304050607080ISTRUMENTSPage 6 of 19SWRA308A98Avg 3.6VAva 3vAvg 2V110111213141516171819202122232425261023.6V-1062V-110-40-30-20-100102030405060708070604020-Wanted signal at:-82 dBm10ISTRUMENTSPage 7 of 19SWRA308ACC2530-CC2591EM High Gain ModeC C2530-CC2591EM Low Gain Mode- CC2530EM40000-100110100908070-60-50-40-30-20-100The IEEE standard 802.15. 4 [8] requires the transmitted spectral power to be less than thelimits specified in table 4.7If-fc>3.5 MHz-20 dB-30 dBmThe results below are given for Tc=25 C, Vdd=3.0V and f= 2440 MHz, and are measuredon the CC2530-CC259 1EM reference design with a 50 Q loadIEEE absoluteChannel 182432.52435243752442524452447.5ISTRUMENTSPage 8 of 19SWRA308AOnly a few external components are required for the CC2530-CC2591 reference design. Atypical application circuit is shown below in Figure 5.1. Note that the application circuit figuredoes not show how the board layout should be done. The board layout will greatly influencethe RF performance of the CC2530-CC2591EM. TI provides a compact CC2530CC2591 EM reference design that it is highly recommended to follow. The layout, stack-upand schematic for the CC2591 need to be copied exactly to obtain good performance. Notethat the reference design also includes bill of materials with manufacturers and part numbersL102 L10=TI INF inductorVDD13cc2530LA 1RF PANTCC2591 RF NFNPA EN(P1 1)i工工I NA FNP:1HGM ENPO 7)T:1Proper power supply decoupling must be used for optimum performance. In Figure 5.1, onlythe decoupling components for the CC2591 are shown. This is because, in addition todecoupling, the parallel capacitors C11, C101, and C131 together with, L101, L102, TL11TL101 and TL131 also work as RF loads. These therefore ensure the optimal performancefrom the CC2591. C161 decouples the AvDD blAs power.The placement and size of the decoupling components, the power supply filtering and thePCB transmission lines are very important to achieve the best performance Details about theimportance of copying the CC2530-CC2591EM reference design exactly and potentialconsequences of changes are explained in chapter 6The RF input/output of CC2530 is high impedance and differential. The CC2591 includes abalun and a matching network in addition to the PA, LNa and RF switches which makes theinterface to the CC2530 seamless. Only a few components between the CC2530 andCC2591 necessary for RF matching For situation with extreme mismatch(VSWR 6: 1 till 12: 1out-of-band as shown in Figure 6.2) it is recommended to include all the components asshown in Figure 5.1ISTRUMENTSPage 9 of 19SWRA308ANote that the PCB transmission lines that connect the two devices also are part of the RFmatching. It is therefore important to copy the distance between the devices, the transmissionlines and the stack-up of the PCB according to the reference design to ensure optimumperformanceThe network between the CC2591 and the antenna(L111, C112, C111 C113 and L112matches the CC2591 to a 50 2 load and provides filtering to pass regulatory demands. C111also works as a dc-blockR151 is a bias resistor the bias resistor is used to set an accurate bias current for internaluse in the cc2591The TI reference design contains two antenna options. As default, the Sma connector isconnected to the output of CC2591 through a 0 Q2 resistor. This resistor can be soldered offand rotated 90 clockwise in order to connect to the PCB antenna, which is a planar invertedF antenna(PIFA). Note that all testing and characterization has been done using the SMAconnector. The PCB antenna has only been functionally tested by establishing a link betweentwo EMs. Please refer to the antenna selection guide [6] and the Inverted F antenna designnote [7 for further details on the antenna solutionsISTRUMENTSPage 10 of 19SWRA308A

计算理论复习总结,但是考试快要结束了，估计大家也没有什么需要了。28.文法是CFG的推广,任何CFG都是文法。G=(V,∑,R,S)29.语言被文法生成ⅲ它是re的。30.所有数值函数都是原始递归的31.原始递归函数集是递归可枚举的。32.特殊语言/问题H={"M"w":M在w上停机}lH={"M"w":M是一台在"w"上不停机的TM}H1={"M":M在“M”上停机}H1={w:要么w不是一台TM的编码,要么w是M的编码,M是一台在"M"上不停机的TM}H:re.;H1:re.;-H,-H1:非r.e.;2-SAT∈P;SAT∈NPThe world as We Dont Know itreAsumming P≠APCo『eHrecursiveSATSATCO-A伊II Asumming P=Npr, eCo-r.erecursiveNP= cO-Np= p33没有算法的问题称作不可判定的or不可解的,如TM的停机问题34.证明不可判定通用图灵机U通过递归函数归约到L如果L是递归的则U是递归的ic若L1非递归,并存在L1到L2的归约,则L2也非递归。递归函数是 Turing Computable的35.语言是图灵可枚举的,证存在枚举它的图灵机。(M通过空格代开始,周期性的经过特殊状态q来枚举L,任意顺序且可重复)6.不可判定语言与递归语言互为补集,与rc语言有交集。37语言是re.,if它是图灵可枚举的;语言是递归的,i它是以字典序 turing可枚举的。8.P在并交连接和补运算下封闭NP在并、连接运算下封闭。若NP在补下封闭则NP=P39.H={M"wM在最多2w步后停机}唾P40.所有正则语言和所有CFL都属于P41.NPA.机器角度去定义:被多项式界限非确定型图灵机判定的所有语言的类。B.基于 verifier的定义:NP问题上建立的非确定机包含两步1)非确定地猜一个解2〕用一个确定的算法判定该解是否为可行解判定一个给定猜测值是否满足该问题(可满足性)的算法称作 verifier,一个问题称作NP问题当且仅当存在一个多项式时间的 verifier这两个定义是不矛盾的,因为如果一台非确定TM在多项式时间内可以判定一个非确定选择的翰入是否满足,就是基于 verifier的定义。P和NP的区别a problem is in P if we can decide them in polynomial time. It is in NP if we candecide them in polynomial time, if we are given the right certificate42.若存在计算函数f的多项式界限的图灵机M,则f称为多项式时间可计算的43.若τ1是L1->l2的多项式归约,τ2是L2->I3的多项式归约,则τ1τ2是L1->l3的多项式归约44.证明NP完全法一、按定义:LΣ*,若(a)L∈NP,且(b)对每个语言L∈NP,存在从L到L的多项式归约则L称为NP完全的。法二、归约,对于语言L,(a)若L∈NP(b)一个NP完全问题可以在多项式时间规约到L,ie. SAT 0 is context-free but not regular49.L=L1L2,L是CFL,则L1一定是CFL(x50. Regular-CFL不一定是CFL,如a*b*c*-anbn包含 anben51. 2-way PDalie PDa whose input heads can move both left and right] are more powerfulthan 1-way pda52. Given a PDa M1 and an fa M2, the problem l(M1)cl(M2)is decidable53.DFA/NFA识别的是 exactly正则语言54.Re.只在补和差下不封闭,CFL在交下也不封闭55.非正则语言的可能是正则语言。比如A:[W=w}及所有回文,A=*,为正则语言56.典型非正则:w=wR57.正则语言的子集可能非正则,如 anben是a*b*c*的子集;又如Σ*是正则语言,H≌Σ*58.归约:X到Y的归约可以理解为X到Y问题的映射, reduction可以解释为 at least asdifficult as….比如ⅹ可以被Y的算法解决,则 X is no more difficult than yⅩ可以约到Y,记X≤Y。e.gx2可以归约到任意两数的乘积。若有A≤B,A是不可判定问题>B不可判定A不递归->B不递归B可判定>A可判定B是递归的->A是递归的59.若X多项式时间归约到Y,Y多项式时间可解,则X多项式时间可解若X多项式时间归约到Y,Ⅹ多项式时间不可解,则Y多项式时间不可解60.X多项式时间归约到Y,Y多项式时间归约到Z,则X多项式时间归约到Z61.PRME( COMPOSITE)多项式时间归约到 Factor,但是 Factor多项式时间不能归约到PRIME COMPOSITE )o62.若A≤PB,B∈NP,则A∈NP。证明A≤PB→存在确定图灵机X,可将A归约到B。B∈NP→存在一个非确定图灵机N可判定B。我们希望构造一个新的TM(ⅹN)是的ⅹ*N非确定多项式时间求解A,则A∈NPRunning time of X*N≤1+p(mB>+qp(m)(B多项式时间非确定判定是多项式时间所以A∈NP63若AsPB,B∈P,则A∈P64.若X是NPC的,则X在多项式时间内可解ifP=NP65.SAT多项式时间归约到3SA(3AT是NPC的)66.证明语言L是R/Re, Non rea) Intuitively想想有没有半判定(判定)的TM,有则Rc、(R)。若非R执行下一步。b)用能否由Re.( Non re.)语言归约到该语言,能则Re而非R( Non re)严格用归约函数定义f:A≤B,r1∈A当且仅当r1∈Beg1∈H,M∈L证明Recg2∈非H,iM∈L证明 Non rc注意方向:是从A的实例经过递归函数推向B的实例。详细介绍http://www.cs.rice.edu/nakhleh/comp481/finalreviewsp06sol.pdf67.递归与μ递归等价68.PDA中,若每一个格局至多有一个格局接在它后面,则为确定型的。确定型CF在补下封闭69.M半判定L:w∈L,ifM在w上停机,注意半判定图灵机中不存在“拒绝”状态。只要不接受w,就不停机。70. Chomsky hierarchyElements of the Chomsky HierarchyRecursively enumerable languagesRecursive languageContext sensitive languagesContext ee languageseterministccontext free languagesRegularanguages71.俩证明7.6证明P在并、交、 Kleene*连接和补运算下封闭(1)并:对任意L,LEP,遴n时间图灵机M1和nb时间图灵机M2判定它们且c=max{ab}对L1L2构造判定器MM=“对于输入字符串w1)在W上运行M1,在w上运行M22)若有一个接受则接受,否则拒绝。时间复杂度:设M1为0(n)M2为0(m)。令c=max{ab}第一步用时0(n+n),因此总时间为Oma+n)=0(n9所以L1L2属于P类,即P在并的运算下封闭。(2)连接对任意L1,L2属于P类,设有n时间图灵机M1和m时间图灵机M2判定它们,且c=max{ab}。对L1l2构造判定器MM=“对于输入字符串w=w2灬,Wn对k=0,1,21…,n重复下列步骤。在wW2…wk上运行M1,在wk1wk+2…n上运行M若都接受,则接受。否则继续。若对所有分法都不接受则拒绝。时间复杂度:(n+1x0(n+0m-0(m+4)+0(nb+4=0(nc+),F以L1oL2属于P类,即P在连接的运算下封闭。对任意L属于P类,设有时间0(n)判定器M判定它,对构造判定器MM=“对于输入字符串〔1)在w上运行M12)若M1接受则拒绝,若M1拒绝则接受。时间复杂度为:0(m)。所以属于P类,即P在补的运算下封闭。77证明NP在并和连接运算下封闭。1)并对任意L1,L2∈NP,设分别有n时间非确定图灵机M1和n时间非确定图灵机M2判定它们,且c=max{a,b}。构造判定LL2的非确定图灵机M:M=“对于输入字符串w1)在W上运行M1,在w上运行M2。2)若有一个接受则接受,否则拒绝。对于每一个非确定计算分支,第一步用时为O(n-)+O(n),因此总时间为On+n)=0(n。所以LLz∈NP,即NP在并的运算下封闭2)连接对任意L,L2∈NP设分别有na时间非确定图灵机M1和m时间非确定图灵机M2判定它们,且c=max{ab}。构造判定L1oL2的非确定图灵机M:M=“对于输入字符串w:1〕非确定地将分成两段xy,使得w=xy。2)在x上运行M1,在y上运行M23)若都接受则接受,否则拒绝。对于每一个非确定计算分支,第一步用时O(n,第二步用时为0(n)+0(m),因此总时间为o(n+m)=0(n。所以L1oL2∈NP,即NP在连接运算下封闭。专题一一图灵机可判定性问题判定以下问题是否可判定:声明:思路—想证明B问题不可解,1.从一个不可解问题A入手(如停机问题)2.创建B的—个实例,从中推出如果能解决B,A也就可以解决了3.所以B是不可解的1.一个图灵机有至少481个状态。我们可以给出这样一个TMN进行cnc(M)a)数M中状态数,直到481b)如果达到了481,N就接受,否则拒绝2.给定图灵机在空串上走了481步还没停机。构造2带图灵机N,a)2a带:写481个0b)1s带在空串上模拟M,每走一步,第2带就删掉一个0c)如果M在所有0都删掉之后停机,则N接受,否则不接受给定图灵机,判定它是否在一些输入上经过481步还没停机?a)按字典序找出所有 length

cyrillic用于家族图谱绘制，简易方便，好实用

中文版！花了不少人民币翻译的，翻译的很靠谱！EtherNet/IP Adaptation of CIP

在网上看到很多网页音乐播放器，做得都很精致漂亮，却看不到它们的代码。我在大学毕业时做的毕业设计——在线音乐网站实现，搜集了很多网页音乐播放器的资料，加上现在的整理，自己做了一个网页音乐播放器。 相关的说明在压缩包的【readme】文件中，希望给予正在开发网页音乐播放器的人员一个参考。

Verilog串口通信程序，详细注释自己看了很多材料以后，精心整理的串口通信实验原理和指导，在网上找了很多代码，大部分因为没有很好的注释，看起来很头疼，于是自己写了一份，附带详细的注释，在modelsim仿真器上已经得到验证，现在传上来，仅供参考。PS1:最后部分给出了一个测试文件，写的非常简单，只是验证了功能，不是很好的测试；PS2：代码部分看上去有点乱，因为在word中代码的层次结构无法清晰显示，如有需要，下载后把代码copy到notepad++这种类似的专用变成工具里面，就很清晰的显示代码和注释了。