多特征融合的目标跟踪

针对水平集算法，李纯明博士的DRLSE改进方法，matlab实现。

德国信用数据（creditcard.csv）

北斗三号新体制多功能可配置双通道采样器SIS800，可支持卫星导航全频点系统频段中频数据采集，基于USB3.0接口上传数据目录第一部分北斗三号新体制多功能可配置双通道采样器SS800-硬件连接说明北斗三号新体制多功能可配置双通道采样器S|S800参数说明二.北斗三号新体制多功能可配置双通道采样器S|s800前后面板介绍三.北斗三号新体制多功能可配置双通道采样器S|S800上电使用说明第二部分北斗三号新体制多功能可配置双通道采样器S|s800USB30驱动程序安装说明…10第三部分北斗三号新体制多功能可配置双通道采样器S|S800-上位机软件安装及使用说明….16上位机软件安装说明…16第四部分基于 Matlab卫星中频信号捕获软件使用说明22采样数据组织格式.22二. Matlab程序使用说明.23第一部分北斗三号新体制多功能可配置双通道采样器S|S800-硬件连接说明北斗三号新体制多功能可配置双通道样器S|S800是上海宇志通信技术有限公司在2018年最新推出的一款支持多卫星导航系统频段的双通道卫星中频信号采样器,数据传输采用USB3.0接口,20MHz/0.01ppm恒温晶振做为设备的同步参考时钟。双通道采样器中的每个通道可灵活配置采集的频段(1.0GHz~20GHz即L波段范围)、带宽(2046MHz~32736MHz,步进2.046MHz,其中32736MHz的带宽支持北斗号新体制信号B1C的系统带宽),两个通道联动设置采样频率(10MHz、20MHz、40MHz)以及数据位宽(4比特、8比特)在使用这款卫星中频信号采样的过程中,需特别提请用户注意的是,S|S800内部采用恒温晶振来做为设备的同步参考晶振,而恒温晶振通常需要有一个预热的过程,因此建议用户预热3~5分钟,即开机3~5分钟后进行样工作。北斗三号新体制多功能可配置双通道采样器S|S800参数说明(1)主要用途卫星导航定位系统软件接收机设计开发姿态测量卫星导航定位系统芯片和接收机设计开发冫卫星导航定位接收机干扰、抗干扰研究导航卫星信号载波相位研究与应用研究导航卫星信号多径下扰研究导航卫星信号分析≯高灵敏度玊星导航接收机搜索与跟踪算法硏究高精度卫星导航接收机算法研究(2)参数设置界面北斗三号新体制多功能可配置双通道平样器-Ss800射频来样通道A参数设置射蜮采样通追B参数设置世使能]来样>使能[函道使能]射频采样通道B使胎[频选择]旧户动频勾段选择]用户手动设置射频参效扎三号B1C频射频载频率176MH(可设范围1.0~2.0GH斗三号B3I频段[信号带宽]八二号B2頻段信号带贸]信号戏边带16+2045NH可设范围116)扌斗是B3频段∈PsL1频段[样速率]PsL2频x-〉[乐样速家]平样速平->4MH(〔频通道与联动设置:EpsL5掀段优岡F1频数据位!时E53频段x=助位究]热提肉4比持〔频函与联动设置)什BE5b频CLONA5L频段初始化操怍区1单击览按钮选择存储文件路径和名(买际生成文件名会在这个文件名基砒上添加厂采样多数「间等泪关辅助信息存储文件名测览2输入仔时间卡度单位:秒)为Q时表示不限时保仔数提3单击保存数据拉钮"开始保存从UB30妄妾收到的数据保存数据4)上位进度0000秒(3)技术指标:●推荐天线基本指标:极化 Polarization:右旋圆极化RHCP天线增益Gain(GBi仰角90度:≥6仰角20度≥0仰角10度:轴比:仰角90度≤3仰角15度≤5相位中心误差(mm):2LNA增益Gain(dBi)40±2驻波比∨SW.R

本资料为作者研究生期间所做研究的总结与整理，主要是利用abaqus的umat子程序实现复合材料的疲劳分析及寿命预测，里面对umat的调用层次作了图示讲解。如需对应umat程序的，可私聊。

The Verilog® Hardware Description Language (Verilog HDL) became an IEEE standard in 1995 as IEEEStd 1364-1995. It was designed to be simple, intuitive, and effective at multiple levels of abstraction in astandard textual format for a variety of design tools, including verification simulation, timiThe clear directive from the users for these three task forces was to start by solving some of the followingproblemsConsolidate existing IeeE Std 1364-1995Verilog generate statementMulti-dimensional arraysEnhanced Verilog file i/oRe-entrant tasksStandardize Verilog configurationsEnhance timing representationEnhance the vpi routinesAchievementsOver a period of four years the 1364 Verilog Standards Group(vsg) has produced five drafts of the lrmThe three task forces went through the EEe Std 1364-1995 lRM very thoroughly and in the process of consolidating the existing Lrm have been able to provide nearly three hundred clarifications and errata for theBehavioral, ASIC, and PLI sections. In addition, the vsg has also been able to agree on all the enhance-ments that were requested (including the ones stated above)Three new sections have been added. Clause 13, "Configuring the contents of a design, deals with configuration management and has been added to facilitate both the sharing of verilog designs between designersand/or design groups and the repeatability of the exact contents of a given simulation session Clause 15Timing checks, "has been broken out of Clause 17, "System tasks and functions, "and details more fullhow timing checks are used in specify blocks. Clause 16, "Backannotation using the Standard Delay Format(SDF), addresses using back annotation(IEEE Std 1497-1999)within IEEE Std 1364-2001Extreme care has been taken to enhance the vpi routines to handle all the enhancements in the behavioraland other areas of the lrm. minimum work has been done on the pli routines and most of the work hasbeen concentrated on the vpi routines. Some of the enhancements in the vpi are the save and restart simu-lation control, work area access, error handling, assign/deassign and support for array of instances, generateand file 1/0Work on this standard would not have been possible without funding from the cas society of the ieee andOpen verilog InternationalThe IEEE Std 1364-2001 Verilog standards Group organizationMany individuals from many different organizations participated directly or indirectly in the standardizationprocess. The main body of the Ieee Std 1364-2001 working group is located in the United States, with asubgroup in Japan (EIAJ/1364HDL)The members of the IEEE Std 1364-2001 working group had voting privileges and all motions had to beapproved by this group to be implemented the three task forces focused on their specific areas and theirrecommendations were eventually voted on by the Ieee Std 1364-2001 working group

西门子SCL中文手册西门子SCL中文手册西门子SCL中文手册

对数字调制信号ASK、FSK、PSK类利用高阶累积量特征进行识别的matlab程序

C++算法大全及面试题详解资料包包含两个word文档，一个C++算法大全，一个C++面试经典题及答案详解（包含大量代码）。这两份资料整理了C++的常见算法、常见考点和重要知识技巧，内容齐全，涵盖各类应试考点，满满干货（代码里程多）。这份精细资料旨在为大家面试面试C++程序员或算法工程师提供一些有用参考。

压缩包内有2个M文件，分别是带端点延拓的EMD分解程序和不带端点延拓的EMD分解程序

二自由度的机器人机械臂控制，属于多变量控制系统，PD，PID等控制方法