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altera公司IP核使用手册,对于学习EDA技术的学生或工程师有用A吉RAContentsChapter 1. About this MegaCore FunctionRelease informat1-1Device Family Support···Introduction.··········FeaturesOpen core plus evaluation1-3Performance···Chapter 2. Getting StartedDesign Flow衡·鲁·,看·,音番2-1Megacore Function walkthrough2-2Create a New quartus II Pi2-2Launch the mega Wizard Plug-in ManagerStep 1: Parameterize2-5Step 2: Set Up SimulationStep 3: Generate..,2-11Simulate the design2-13Compile the design2-13Pa Device2-14Set Up Licensing2-15ppend the license to yourdat file2-15Specify the License File in the Quartus II Software...2-15Example Simulation and Compilation..2-16Example quartus Ii project2-16Example simulation with Test Vectors,,,,,,2-16Chapter 3. SpecificationsyperTransport Technology Overview1HT SyStems3-2HT Flow ControlHyper Transport MegaCore Function SpecificationPhysical InterfaceSynchronization and alignment ...Protocol interfClocking Options.......HyperTransport Mega Core Function Parameters and HT Link Performance3-10Signals3-14CSR Module...3-31OpenCore plus time-Out BehaviorAppendix A. ParametersIntroduction鲁鲁鲁A-1Parameter listsDevice Family and Read Only registers···········,,,,,,,,,,A-1Base Address Registers番鲁,A-2Clocking OptionsA-3Advanced settingso March 2009 Altera corporationHyperTransport MegaCore Function User GuideAppendix B. Stratix Device Pin AssignmentsIntroductionB-1GuidelinesAppendix C. Example designGeneral descriptionAdditional informationRevision historyInto-lHow to Contact alteraInfo-1Typographic Conventions ..........Info-2Hyper Transport MegaCore Function User Guideo March 2009 Altera CorporationA吉RA1. About this MegaCore FunctionRelease InformationTable 1-1 provides information about this release of the Hyper Transport Mega CoretfunctioTable 1-1. Hyper Transport Mega Core Function Release InformationitenlDescription∨ ersion9.0Release dateMarch 2009Ordering codeIP-HTProduct ID(s)0098Vendor iD(s)6AF7Altera verifies that the current version of the quartus@ll software compiles theprevious version of each MegaCore function. Any exceptions to this verification arereported in the Mega Core lP Library release Notes and Errata. Altera does not verifycompilation with Mega Core function versions older than one releaseDevice Family SupportMegaCore functions provide either full or preliminary support for target Alteradevice families:Full support means the Mega Core function meets all functional and timingrequirements for the device family and may be used in production designsa Preliminary support means the Mega Core function meets all functionalrequirements, but may still be undergoing timing analysis for the device family;itmay be used in production designs with cautionTable 1-2 shows the level of support offered by the Hyper Transport MegaCorefunction for each of the altera device familiesTable 1-2. Device Family SupportDevice FamilySupportHard Copy Stratix@FullStratixFulStratix IIFulStratix‖GXPreliminaryStratix GXOther device familiesNo supportC March 2009 Altera CorporationHyperT ransport Mega Core Function User Guide1-2Chapter 1: About this MegaCore FunctionIntroductionIntroductionThe Hyper Transport Mega Core function implements high-speed packet transfersbetween physical(PhY) and link-layer devices, and is fully compliant with theHyperTransport l/O Link Specification, Revision 1.03. This Mega Core function allowsdesigners to interface to a wide range of Hyper TransportTm technology(hT)enableddevices quickly and easily, including network processors, coprocessors, videochipsets, and ASICsFeaturesThe Hyper Transport Mega Core function has the following features8-bit fully integrated hT end-chain interfacePacket-based protocolDual unidirectional point-to-point linksUp to 16 Gigabits per second(Gbps)throughput(8 Gbps in each direction)200, 300, and 400 MHz DDR links in Stratix and Stratix GX devices200, 300, 400, and 500 MHz ddr links in Stratix II and Stratix II GX devicesLow-swing differential signaling with 100-Q2 differential impedanceHardware verified with Hyper fransport interfaces on multiple industry standardprocessor and bridge devicesFully parameterized mega core function allows flexible, easy configurationFully optimized for the altera stratix Il, Stratix, Stratix GX, and Stratix II GXevice famillesApplication-side interface uses the Altera AtlanticTM interface standardManages Hr flow control, optimizing performance and ease of useIndependent buffering for each HT virtual channelAutomatic handling of ht ordering rulesStalling of one virtual channel does not delay other virtual channels(subject toorderingFlexible parameterized buffer sizes, allowing customization depending onsystem requirementsUser interface has independent interfaces for the HT virtual channels, allowingindependent user logic designCyclic redundancy code(crc) generation and checking to preserve data integrityIntegrated detection and response to common HT error conditions■ CRC errorsEnd-chain errorsFully integrated HT configuration space includes all required configuration spaceregisters and HT capabilities list registersHyper Transport MegaCore Function User Guideo March 2009 Altera CorporationChapter 1: About this MegaCore FunctionPerformance32-bit and 64-bit support across all base address registers bars)automatically handles all csr space accessesVerilog HDL and VHdL simulation supportOpen Core Plus EvaluationWith the Altera free Open Core Plus evaluation feature, you can perform the followingSimulate the behavior of a mcgafunction(Altera MegaCore function or AMPPmegafunction) within your systema Verify the functionality of your design, as well as quickly and easily evaluate itssize and speedGenerate time-limited device programming files for designs that includeMegaCore functionsProgram a device and verify your design in hardwareYou only need to purchase a license for the Mega Core function when you arecompletely satisfied with its functionality and performance and want to take yourdesign to productiono For more information about Open Core Plus hardware evaluation using theHyperTransport MegaCore function, refer to"Open Core Plus Time-Out Behavior"onpage 3-40 and AN 320: Open Core Plus Evaluation of megafunctionsPerformanceThe Hyper Transport Mega Core function uses 20 differential I/O pin pairs and 2single-ended I/O pins, requiring 42 pins total. Table 1-3 through Table 1-5 showtypical performance and adaptive look-up table (alut) or logic element (LE)usagefor the HyperTransport MegaCore function in Stratix II GX, Stratix IL, Stratix, andStratix GX devices respectively, using the Quartus@ II software version 7.1Table 1-3 shows the maximum supported data rates in megabits per second(Mbps)by device family and speed gradeTable 1-3. Maximum Supported Hyper Transport Data Rates (Note 1)Speed GradeDevice Family-36Stratix ll GX devices 1000 Mbps 1000 Mbps 800 MbpsNA(2)N/A(2NA(2)Stratix devices1000 Mbps 1000 Mbps 800 Mbps N/A(2)NA(2)NA(2)Stratix devicesN/A(2N/A(2)00 Mbps 800 Mbps 600 Mbps400 MbpsFlip-Chip packagesStratix devicesNA(2)NA(2)NA(2)600 Mbps400 Mbps400 Mbps(Wire Bond packagesStratix GX devicesN/A(2) N/A(2)800 Mbps 800 Mbps 600 Mbps N/A(2)Notes to table 1-3(1)Rates are per interface bit. Multiply by eight to calculate the uni-directional data rate of an 8-bit inter face(2) Devices ot this speed grade are not ottered in this device familyC March 2009 Altera CorporationHyperTransport Mega Core Function User GuideChapter 1: About this MegaCore FunctionPerformanceTable 1-4 shows performance and device utilization for the Hyper TransportMegaCore function in Stratix II and Stratix II GX devicesTable 1-4. Hyper Transport Mega Core Function Performance in Stratix ll and Stratix ll GX DevicesParametersMemoryUserRXCombinationalHT Link InterfacePosted Non-Posted Response ClockingALUTSLogicfMAX(MHz) MAx(MHz)Buffers BuffersBuffers Option(12)Registers M4K M512 ( 3)3)Shared3.5005200120500125(4RX/TX/Ref35005200500Ref/x8Shared36005400160500>150RX/TXShared4.0006,00016150RX/TX16Shared4,1006,200500125(4)RX/TX/RefShared4.1006200500125(4Ref/TxShared4.2006400160150RX/TXNotes to table 1-4.Refer to " Clocking Options "on page 3-7 for more information about these options(2 )Other parameters(BAR configurations, etc. )vary the alut and Logic Register utilization numbers by approximately +/-200(3)Figures for -3 speed grade devices only(4) When using the Shared Rx/Tx/Ref and Shared Ref/Tx options, the user interface frequency is limited to exactly the ht frequency divided byTable 1-5 shows performance and device utilization for the Hyper TransportMegaCore function in Stratix and Stratix GX devicesTable 1-5. Hyper Transport Mega Core Function Performance in Stratix and Stratix GX DevicesUser Interface fmaxParametersUtilizationHT Link fMAX MHz)MHZ)RXRXSpeed GradePosted Non-Posted Response Clocking Option LEsM4KBuffers BuffersBuffers)(2 Blocks.5-66Shared rx/tx/ref1240010073)100734448888Shared Ref/Tx 7, 60014400400100{3)100(3)Shared rxtx7,90016400400>125>100Shared rxtx8.900125>100168Shared Rx/T×Ref9,400124004001003)100316Shared ref/ ix9.500144001003)10073)16Shared rx/x9.700400125Notes to table 1-5:(1)Refer to Clocking Options"on page 3-7 for more information about these options(2 )Other parameters( BAR configurations etc. )vary the LE utilization by approximately +/-200 LES(3 )When using the Shared Rx/Tx/ Ref and Shared Ref/Tx options, the user interface frequency is limited to exactly the hT frequency divided by fourHyper Transport MegaCore Function User GuideC March 2009 Altera CorporationA吉RA2. Getting StartedDesign FlowTo evaluate the HyperTransport Mega Core function using the Open Core Plus feature,include these steps in your design flowObtain and install the HyperTransport Mega Core functionThe HyperTransport Mega Core function is part of the MegaCore IP Library, which isdistributed with the Quartus ii software and downloadable from the altera websitewww.altera.como For system requirements and installation instructions, refer to Quartus II InstallationLicensing for Windows and Linux Workstations on the Altera website atwww.altera.com/literature/lit-qts.ispFigure 2-1 shows the directory structure after you install the HyperTransportMegaCore function, where is the installation directory. The default installationWindows is C: altera ; on Linux it islopt/alteraFigure 2-1. Directory StructureInstallation directorypContains the Altera MegaCore IP Library and third-party IP coresalteraContains the Altera MegaCore IP LibrarycommonContains shared componentshtContains the Hyper Transport Hyper Transport Megacore function files and documentationdocContains the documentation for the Hyper Transport MegaCore functionlibContains encrypted lower-level design filesexampleContains the design example for the Hyper Transport Mega Core function2. Create a custom variation of the Hyper Transport Mega Core function3. Implement the rest of your design using the design entry method of your choice4. Use the IP functional simulation model to verify the operation of your designo For more information about Ip functional simulation models, refer to the SimulatingAltera IP in Third-Party Simulation Tools chapter in volume 3 of the Quartus II Handbook5. Use the Quartus II software to compile your designC March 2009 Altera CorporationHyperT ransport Mega Core Function User Guide2-2Chapter 2: Getting StartedMega Core Function WalkthroughIg You can also generate an Open Core Plus time-limited programming file,which you can use to verify the operation of your design in hardware6. Purchase a license for the hypertransport Mega Core functionAfter you have purchased a license for the Hyper transport mega Core functionfollow these additional steps1. Set up licensing2. Generate a programming file for the Altera device(s)on your board3. Program the Altera device(s)with the completed designMegaCore Function WalkthroughThis walkthrough explains how to create a custom variation using the AlteraHyper Transport IP Toolbench and the Quartus II software, and simulate the functionusing an ip functional simulation model and the modelsim software when you arefinished generating your custom variation of the function, you can incorporate it intoⅴ our overall projectIe IP Toolbench allows you to select only legal combinations of parameters, and warnsou of any invalid configurationsIn this walkthrough you follow these stepsCreate a New Quartus II Projecta Launch the MegaWizard Plug-in Manager■Step1: Parameterizea Step 2: Set Up Simulation■Step3: Generate■ Simulate the designTo generate a wrapper file and Ip functional simulation model using default values,omit the procedure described in"Step 1: Parameterizeon page 2-5Create a New Quartus ll ProjectCreate a new Quartus II project with the New Project Wizard, which specifies theworking directory for the project, assigns the project name, and designates the nameof the top-level design entityTo create a new project, perform the following steps1. On the Windows Start menu, select Programs> Altera> Quartus II tostart the Quartus lI software. Alternatively, you can use the Quartus II Web editionsoftware2. In the Quartus II window, on the File menu, click New Project Wizard. If you didnot turn it off previously, the New Project Wizard Introduction page appears3. On the New Project Wizard Introduction page, click NextHyper Transport MegaCore Function User Guideo March 2009 Altera Corporation

检测估计和调制理论作者简介　　Harry L.Van Trees 美国麻省理工学院电子工程系教授，曾担任美国空军首席科学家、美国国防通信署首席科学家等要职。 　迄今为止，本书仍然是公认的关于检测、参数估计和线性与非线性调制波形估计方面的一本论述详尽、深入、成功的著作。也是一本较好的研究生教材。内容是研究发生在通信、雷达和声纳中被噪声污染了的各种线性与非线性调制、随机与非随机波形的最佳处理的数学方法和物理结构，各种系统可能达到的性能极限和影响它的各种因素。全书包括导论、经典检测和估计理论、随机过程的描述、信号检测与信号参数估计、连续波估计、线性估计和讨论等7章。每章附有相当数量的扩大内容

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[原创]根据C.Gosselin的论文编写的6-SPS并联机器人可达工作空间绘制程序，思路、算法与数据均来自论文"Determination of the Workspace of 6-DOF Parallel Manipulators"，算法的实现（如圆弧求交离散，可达工作空间边界判定等）由本人自己编写，最后绘制的图形不仅包括z向横截面的工作空间轮廓图，还包括过z轴平面与工作空间的交线，以通过线框图更好的反映工作空间外形。文件中还包括了论文中提到的计算z向截面面积的函数，执行主程序workspace_main.m后输出的AREA第一列为截面面积，第二列为截面的z向位置。

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