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88E1116R_Datasheet

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88E1116R_Datasheet,marvell以太网phy芯片手册,全本88E1116RM A RV E LL. Alaska Gigabit Ethernet TransceiverOVERVIEWFEATURESThe Alaska 88E1116R Gigabit Ethernet Transceiver is10/100/1000BASE-TIEEE 802.3 complianta physical layer device containing a single GigabitSupports reduced pin count GMII(RGMID)interfaceEthernet transceiver. The transceiver implements theFour RGMii timing modesEthernet physical layer portion of the 1000BASE-T,100BASE-TX. and 10base-t standards. t is manufacIntegrated mdi interface termination resistors thateliminate twelve passive componentstured using standard digital CMOS process and con-tains all the active circuitry required to implement theEnergy Detect and Energy Detect+ low powerphysical layer functions to transmit and receive data onmodesstandard Cat 5 unshielded twisted pairThree loopback modes for diagnosticsThe 88E1116R device has two regulators to generateDownshift"mode for two-pair cable installationsall required voltages. The 88E1116R device can beFully integrated digital adaptive equalizers, echopowered by a single 1.8V, 2.5V, or 3. 3V supply Alternacancellers, and crosstalk cancellerstively, if the regulators are not used, then the 88E1116RAdvanced digital baseline wander correctiondevice can be powered by a 1. 8v and 1.2V supplyAutomatic MDi/MDIX crossover at all speeds ofThe 88E1116R device incorporates the Marvell@ VirtualoperationCable Tester (VCTTM)feature, which uses TimeAutomatic polarity correctionDomain Reflectometry(TDR)technology for the remotelEEE 802. 3u compliant Auto-Negotiationidentification of potential cable malfunctions, thusSoftware programmable LEd modes including LEDreducing equipment returns and service calls. UsingtestingVCT, the alaska 88E1116R device detects and reportspotential cabling issues such as pair swaps, pair polar-Supports IEEE 1149.1 JTAGity and excessive pair skew. The device will also detectMDC/MDIO Management Interfacecable opens, shorts or any impedance mismatch in theCRC checker, packet countercable and reporting accurately within one meter the disPacket generationtance to the faultVirtual Cable Tester(VCT)The 88E1116R device integrates MDI interface terminaAuto-Calibration for MAc Interface outputstion resistors into the Phy. this resistor integrationComa Mode supportfacilitates board layout and reduces board cost byRequires a single 1.8v supplyreducing the number of extenal components. The new10 pads can be supplied with 1.8V, 2.5V, or 3. 3VMarvell calibrated resistor scheme will achieve andexceed the accuracy requirements of the IEEE 802.3Two regulators generate all required voltagesRegulator can be supplied with 1.8V,2.5V or 3.3Vreturn loss specificationsCommercial gradeThe 88E1116R device supports the reduced gmll64-Pin QFN package(RGMI)for direct connection to a MAC/Switch portThe 88E1116R device uses advanced mixed-signal processing to perform equalization, echo and crosstalkcancellation, data recovery, and error correction at agigabit per second data rate. The device achievesrobust performance in noisy environments with very lowpower dissipationThe 88E 1116R device is offered in a 64-pin QFn pack-The 88E1116R device is footprint compatible with the88E1116 device As the 88E 1116R device employs integrated MDi interface terminations, all external mDIinterface termination resistors and capacitors must beremoved when migrating from the 88E1116 to88E1116R. See 88E1116 to 88E1116R Migration Appli-cation note for more detailsCopyright o 2007 MarvellCONFIDENTIALDoC. No. MV-S104224-00. Rev.March 1. 2007. AdvanceDocument Classification: Proprietary InformationPage 388E1116RMARVELLo Alaska Gigabit Ethernet TransceiverMagnMedia Types10/1001000Mbps88E1116R|a盖10BASEEthernet macRJ-45Device100BASE-TX1000BASE-TMAC InterfaceRGMII88E1116R Device used in Copper ApplicationDoc. No. MV-S104224-00. Rev.CONFIDENTIALCopyright o 2007 MarvellPage 4Document Classification: Proprietary InformationMarch 1. 2007. AdvanceTable of contentsSECTION 1. SIGNAL DESCRIPTION1.1 Pin Description101.1.1 Pin Type Definitions1264 Pin QFN Pin Assignment List- Alphabetical by Signal Name.……,…,,…,161.3 O State at Various Test or reset modes .mmm.,17SECtION 2. FUNCTIONAL SPECIFICATIONS2.1 Copper Media Interface..国面画192.2 MAC Interface(RGMII)4192.2.1 10/100 Mbps Functionality2.2.2 TX ER and RX ER Codingaaaaaiiaia t23Lo。 pback……………,….….….,.,…….…,…,….….……,…….……………212.3.1 MAC Interface Loopback212.3.2 Line Loopback.222.3.3 EXternal Loopback24 Synchronizing F|FQ….…,,…,…,,,,,,…,,,,,…,,,…,,,,…,……242.5 Copper Media Transmit and receive Function.man..m日a252.5.1 Transmit side Network Interface252.5.2 Encoder2.5.3 Receive Side Network Interface2.5. 4 Decoder2.6 Regulators and Power Supplies282.6.1 AVDD2.6.2 AVDDC282.6.3 AVDDR292.6.4 AVDDX2.6.5DVDD…292.6.6 VDDO26.7 VDDOR.292.7 Power Management302.7.1 Low Power Modes2.72 Low Power Operating Modes……2.7.3 RGMl Effect on Low Power modes3228Auto- Negotiation.........……33Copyright o 2007 MarvellCONFIDENTIALDoC. No. MV-S104224-00. Rev.March 1. 2007. AdvanceDocument Classification: Proprietary InformationPage 588E1116RMARVELL Alaska Gigabit Ethernet Transceiver2.9 Downshift Feature…352.10 Advanced virtual Cable Tester362.10.1 Maximum Pe2.10.2 First Peak372.10.3 Offsetp2. 10. 4 Sample Poin2.10.5 Pulse Amplitude and Pulse Width392. 10.6 Drop Link...392.10.7 VCTTM With Link Up392.11 Data Terminal Equipment (DTE)Detect........2.12 CRC Error Counter and frame Counter412.12. 1 Enabling the crc error counter and frame counter.412.13 Packet generator412.14 MDI/MDIX Crossover422.15P。 olarity Correction..…432.16LED,,,,,,,,,,,…,…,,442.16.1 LED Polarity452.16.2 Pulse Stretching and Blinking.462. 16.3 Bi-Color LED Mixing472.16.4 Modes of Operation482.17 EEE 1149.1 Controller522.17.1 BYPASS Instruction522.17.2 SAMPLE/PRELOAD Instruction.52217.3 EXTEST Instruction552,17.4 The clamP Instruction552,17.5 The high-z Instruction552.17.6 ID CODE Instruction552.18 Interrupt.552.19 Automatic and Manual Impedance Calibration.……,…,…,…,…,…,…,……562. 19. MAC Interface calibration circuit562.19.2 MAC Interface Calibration Register Definitions2. 19.3 Changing Auto Calibration Targets2. 19. 4 Manual Settings to The Calibration Registers“““582.20 Configuring the 88E1116R Device..2.20. 1 Hardware Configuration612.20.2 Software Configuration-Management Interface632.21 Temperature sensor64Doc. No. MV-S104224-00. Rev.CONFIDENTIALCopyright o 2007 MarvellDocument Classification: Proprietary InformationMarch 1. 2007. AdvanceSECTION 3 REGISTER DESCRIPTION65SECTION 4, ELECTRICAL SPECIFICATIONS1104.1. Absolute Maximum Ratings,…,…,…,…,,…,…,…,…,…,…,,…,…,……,1104.2. Recommended Operating Conditions..,,.,……,,……1114.3. Package Thermal Information.………….……….…………1124.3.1 Thermal Conditions for 64-pin QFn Package1124. 4. Current Consumption...........面量量…1134.4.1 Current Consumption AVDD..1134.4.2 Current Consumption AVDDC..1134.4.3 Current Consumption AVDDR1144.4.4 Current Consumption AVDDX1144.4.5 Current Consumption DVDD4.4.6 Current Consumption VDDo1154.4.7 Current Consumption VDDOR1154.4.8 Current Consumption Center Tap1154.5. DC Operating Conditions1164.5.1 Non-RGMlI Digital Pins1164.5.2 Internal resistor Description4.5.3 Stub-Series Transceiver LogIc (55/.21174.5 4 EEE DC Transceiver Parameters1194.6. AC Electrical Specifications1204.6.1 Reset Timing ..1204.6.2 XTAL IN/XTAL OUT Timing1214.6.3 LED to CONFIG Timing1214.7 RGMII Interface Timing……,,…1224.7.1 RGMl AC Characteristics4.7.2 RGMII Delay Timing for different RGMiI Modes1234.8. MDC/MDIO Timing…12549. JTAG Timing…,,…1264.10.EEE AC Transceiver parameters1274.11. Latency Timing........….…1284.11.1 RGMII to 1000BASE-T Transmit Latency Timingaa“aa1284.11.2 RGMII to 100BASE-TX Transmit Latency Timing1284.11.3 RGMiI to 10BASE-T Transmit Latency Timing4. 11. 4 1000BASE-T to RGMll Receive Latency Timing1304. 11.5 100BASE-TX to RGMII Receive Latency Timing.1304.11.610 BASE-T to RGMll Receive Latency Timing……….….…………,130SECTION 5. PACKAGE MECHANICAL DIMENSIONS1315.1 64-Pin QFN Package...131Copyright o 2007 MarvellCONFIDENTIALDoC. No. MV-S104224-00. Rev.March 1. 2007. AdvanceDocument Classification: Proprietary InformationPage 788E1116RMARVELL Alaska Gigabit Ethernet TransceiverSECTION 6. ORDER INFORMATION1336.1 Ordering Part Numbers and Package Markings1336.1.1 RoHS 5/6 Marking Example1346.1.2 RoHS 6/6 Marking Example135Doc. No. MV-S104224-00. Rev.CONFIDENTIALCopyright o 2007 MarvellPage 8Document Classification: Proprietary InformationMarch 1. 2007. AdvanceSignal DescriptionSection 1. Signal DescriptionThe 88E1116R device is a 10/100/1000BASE-T Gigabit Ethernet transceiverFigure 1: 88E1116R Device 64-Pin QFN Package(Top view)文gg9廿廿廿廿廿廿凵廿廿廿凵廿守令导好寸守哥导$85#將RX CTRL4932TSTPTRXDIO5031MDIPIORXD[51EPAD-VSS30d MDIN[O]VDDOR52290 AVDDRX CLK5328叫NCRXD[2]54AVDDRXD]5526MD|P[1VDDOR56VREF57MARVEL L③24E MDIP[2TXD0]□5823MDIN[2TXD[1]B5988E1116R22AVDDTX_CLK F6021AVDDTXD[2Top ViewMDIP[3TXD3]□62190 MDIN[3]TⅩCTRL6318□NCCONFIG[O]64CTRL18三s回口cc×O百口口艺艺安安Copyright o 2007 MarvellCONFIDENTIALDoc. No. MV-S104224-00 RevMarch1.2007. AdvanceDocument Classification: Proprietary InformationPage 988E1116RMARVELL. Alaska Gigabit Ethernet Transceiver1.1 Pin Description1.1.1 Pin Type DefinitionsPin Ty peDefinitionHInput with hysteresisVOInput and outputInput onlOutput onlPUIntemal pullPDInternal pull downOpen drain outputTri-state outputADC sink capabilityDoC. No. MV-S104224-00 RevCONFIDENTIALCopyright o 2007 MarvellPage 10Document Classification: Proprietary InformationMarch.2007. Advance

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Black Box System object4-21Use System object In MATLAB Design Function4-23Generate HDL Code4-23limitations for hdl. black box4-26Enable matLab function block generation4-27Requirements for MaTLAB Function Block Generation 4-27Enable matlab function block generation4-27Results of matlab function block generation4-27System Design with HDL Code Generation fromMATLAB and simulink4-28Generate Xilinx System Generator Black Box Block4-32Requirements for System Generator Black Box BlockGeneration4-32Enable System Generator black Box block GeResults of System Generator Black Box Bloc neration4-32Generation4-33Generate Xilinx System Generator for DsP black boxfrom MATLAB HDL Design4-34Generate HDL Code from MATLAB Code Using theCommand line interface4-40Specify the Clock Enable rate4-45Why specify the clock Enable rate?4-45How to Specify the clock Enable rate4-45Specify Test Bench Clock Enable Toggle rate4-47When to Specify Test Bench Clock Enable Toggle rate4-47How to Specify Test Bench Clock Enable Toggle rate4-47Generate an HDL Coding Standard report fromMATLAB4-49Using the hdl Workflow advisor4-49Using the Command Line4-51Generate an HDL Lint Tool script4-53How To generate an hdl lint Tool Script4-53ContentsGenerate a Board-Independent Ip core from MATLAB 4-55Generate a board-Independent Ip core4-55Requirements and Limitations for IP Core generation4-57Minimize clock enables4-58Using the GUi4-59Using the Command Line4-59Limitations4-59VerificationVerify Code with HDL Test Bench5-2Generate Test bench with file i/oWhen to Use file i/o In Test bench5-5How Test bench generation with file i/o works5-5Test Bench Data files5-5How to generate Test bench with file i/o5-6Limitations When Using File 1/0 In Test Bench5-6DeploymentGenerate Synthesis Scripts6-2Optimization7RAM Mapping7-2Map persistent Arrays and dsp. Delay to RAM7-3How To Enable RaM Mapping7-3RAM Mapping requirements for Persistent Arrays andSystem object PropertiesRAM Mapping Requirements for dsp. Delay Systemob7-6RAM Mapping Comparison for MATLAB Code7-8Pipelining7-9Port registers7-9Input and Output Pipeline registers7-9Variable pipelining7-9Register Inputs and Outputs7-10Insert Input and Output Pipeline registers7-11Distributed Pipelining7-12What is Distributed Pipelin7-12Benefits and Costs of Distributed pipelining7-12Selected Bibliograph7-12Pipeline matlab variables7-13Using the hdl Workflow Advisor7-13Using the Command Line Interface7-13Limitations of MatlAB Variable Pipelining7-13Optimize MatLAb loops7-15oop Streaming7-15Loop unrolling7-15How to Optimize maTLaB loops7-15Limitations for MaTLAB Loop Optimization7-16Constant Multiplier optimization7-17Specify constant multiplier optimization7-19Distributed Pipelining for Clock Speed Optimization7-20Map Matrices to Block RAMs to Reduce Area7-27Resource Sharing of Multipliers to Reduce Area7-32Loop streaming to Reduce Area7-41Contents
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