全志 F1C600完整手册
The F1C600 processor represents Allwinner’s latest achievement in mobile applications processors. The processor targets the needs of boombox markets. F1C600 processor is based on the ARM9 CPU architecture with a high degree of functional integration. F1C600 supports Full HD video playback, iAllwinnerTechnologyRevision HistoryRevision historyVersionateDescriptionV1.0NoV10,2015nitia|Re|ease∨ersⅰonF10600 User Manual( Revision 1.0)Copyright O2015 Allwinner Technology. Co, Ltd. All Rights ReservedPage 3AllwinnerTechnologyRevision HistoryTable of contentsDeclaration2Revision histeD。着,着垂Table of contents.:::::.:::::1:4Chapter 1.About This Documentation361.1 Documentation overview36Chapter 2 Overview....372.1 Processor features2.1.1, CPU Architecture2.2. Memory Subsystem....................382.2.1. Boot rom382.2.2 SDRAM382.2.3. SD/MMC Interface..:::··:·.:::::..:·.:::::::::::··:382.3. System Peripheral.382.3.1. Timer.382.3.2.|NT392.3.3.CCU392.3.4.DMA,392.3.5.PWM,392.4. Display subsystem39241. Display engine…,,…...:::::392.4.2. Display output.....39F10600 User Manual( Revision 1.0)Copyright O2015 Allwinner Technology. Co, Ltd. All Rights ReservecPage 4AllwinnerTechnologyRevision History2.5. Video Engine26.| mage Subsystem…D看看1,翻看、·着国,着,,,面面,2.6.1.CS|4看402.6. 2 CVBS Input402. 7. Audio Subsystem2.7.1, Audio codec2.8. System Peripherals2.8.1.USB2.00TG412.8.2. KEYADC412.8.3.Tl:::::412.8.4. Digital Audio Interface.....................2.8.5.UART412.8.6.SP412.8.7.TW|422.8.8.CIR422.8.9,RSB422.8.10.OWA.422.9 Package422.10. System block Diagram43Chapter3. System..........................,443.1. Memory Mapping….453.2. CCU2463.21 Overy3.2.2, FeatureF10600 User Manual( Revision 1.0)Copyright O2015 Allwinner Technology. Co, Ltd. All Rights ReservecPage 5AllwinnerTechnologyRevision History3.2.3. Functionalities Description3.23.1. System bus….:.:::..a...:::::::非3.23.2 Bus clock tree473.2.4. CCU Register List…….473.2.5. CCU Register Description483.2.5. 1 PLL CPU Control Register3.2.5.2. PLL AUDIO Control register......................493.2.5.3. PLL VIDEO Control Register503.2.5.4. PLL VE Control Register513.2.5.5. PLL DDR Control Register3.2.5.6. PLL PERIPH Control Register...............523.2.5.7. CPU Clock Source register533.2.5.8. AHB/APB/HCLKC Configuration Register543.2.5.9. Bus Clock Gating Register O.......553.2.5. 10. Bus Clock Gating Register 1................553. 2.5.11. Bus Clock Gating Register 2563.2.5.12. SDMMCO Clock Register583.2.5.13. SDMMCl Clock Register.58325.14. DAUDIO Clock Register……593.2.5.15. OWA Clock Register.........................593.2.5.16. CIR Clock Register.603.2.5.17. USBPHY Clock Register603.2.5. 18 DRAM Gating register.603.2.5. 19 BE Clock Register61F10600 User Manual( Revision 1.0)Copyright O2015 Allwinner Technology. Co, Ltd. All Rights ReservecPage 6AllwinnerTechnologyRevision History3.2.5.20. FE Clock Register623. 2.5.21. TCON Clock Register623.2.5.22. De-interlacer Clock Register623.2.5.23. TVE Clock Register∴633.25.24. TVD Clock Register……643.2.5.25. CSI Clock Register643.2.5.26. VE Clock Register.......653.2.5.27. AUDIO CODEC Clock Register653.2.5.28. AVS Clock Register.653.2.5.29. PLL Stable Time register 0653.2.5.30. PLL Stable Time Register 1...............................................................653.2.5.31. PLL CPU Bias register663.2.5.32. PLL AUDIO Bias Register663.2.5.33. PLL VIDEO Bias Register663.2.5. 34 PLL VE Bias Register673.2.5.35.PLL_ DDR Bias Register…..,…,…,…673.2.5.36.PLL_PER| PH Bias Register……673.2.537.PLL_ CPU Tuning Register.……683.2.5.38. PLL DDR Tuning Register683.2.5.39. PLL AUDIO Pattern Control register........................693.2.5.40. PLL VIDEO Pattern Control Register.693.2.5. 41. PLL DDR Pattern Control Register3.2.5.42. Bus Software Reset Register O..3.2.5.43. Bus Software Reset register 1F10600 User Manual( Revision 1.0)Copyright O2015 Allwinner Technology. Co, Ltd. All Rights ReservecPage 7AllwinnerTechnologyRevision History3.2.5.44. Bus Software Reset Register 23.2.6. Programming guidelines3.2.6.1.PLL4看3.2.6.2.BUS3.3. Timer743.3 1. Overvi翻着看743.3.2, Feature…743.3.3. Functionalities Description..743.3.3.1. Typical Applications743.3.3.2. Functional block Diagram753.3.4.Timer Register List.......................753.3.5. Timer Register Description3.3.5.1. Timer IRQ Enable Register...763.3.5.2. Timer iRQ Status Register3.3.5.3. Timer 0 Control Register3.3.5.4. Timer o Interval value register .................................3.3.5.5. Timer 0 Current Value Register3.3.5.6. Timer 1 Control Register....3.3.5.7. Timer 1 Interval value register,7933.58. Timer1 Current Value Register…....…793.3.5.9. T imer 2 Control register3.3.5.10. Timer 2 Interval value Register803.3.5. 11 Timer 2 Current Value register3.3.5. 12 AVS Counter Control Register81F10600 User Manual( Revision 1.0)Copyright O2015 Allwinner Technology. Co, Ltd. All Rights ReservedPage 8AllwinnerTechnologyRevision History3.3.5.13. AVS Counter O Register.81335.14. AyS Counter1 Register.,,…,;…,…,…,…813.3.5.15. AVS Counter Divisor Register….,.,,,,…,,…3.3.5.16. Watchdog irQ Enable Register.………823.3.5.17. Watchdog statusster823.3.5.18. Watchdog Control Register83335.19. Watchdog Configuration Register……,,,…833.3.5.20. Watchdog Mode register....833.3.6. Programming Guidelines843.3.6.1. Timer,,84336.2. Watchdog….…843. 4, PWM853.4.1. Overview853.4.2 Feature853.4.3. Functionalities Description853. 1. Functional Block Diagram......着,着面853.4.4. Operation Principle863. 4.4.1. PWM output pins863.4.5. PWM Register List……3.4.6. PWM Register Description.....................3.4.6.1. PWM Control Register.3.4.6.2. PWM Channel 0 Period Register883.4.6.3. PWM Channel 1 Period register893.5.NTC.90F10600 User Manual( Revision 1.0)Copyright O2015 Allwinner Technology. Co, Ltd. All Rights ReservedPage 9AllwinnerTechnologyRevision History3.5.1. Overview903.5.2, Feature.:..:.:::::a:::.:::.:.a..:::::.:::::903.5.3. Functionalities Description903.5.3.1. Functional Block Diagram903.5.4.Interrupt source913.5.5. INTC Register List.....................................3.5.6. INTC Register Description…923.5.6.1. Interrupt Vector Register.……923.5.6.2. Interrupt base Address register933.5.6.3. NMI Interrupt Control Register933.5.6.4. Interrupt irQ Pending register o933.5.6.5. Interrupt iRQ Pending register 1...............933.5.6.6. Interrupt Enable register o933.5.6.7. Interrupt Enable Register 1.............933.5.6.8. Interrupt Mask register 0943.5.6.9. Interrupt Mask Register 1.::::943.5.6.10. Interrupt Response Register O.......943.5.6.11. Interrupt Response Register 1943.5.6.12. Interrupt Fast Forcing register 0943.5.6.13. Interrupt Fast Forcing Register 1....................................................................953.5.6. 14 Interrupt Source Priority Register O953.5.6.15. Interrupt Source Priority Register 1...973.5.6.16. Interrupt Source priority register 21003.5.6. 17 Interrupt source priority register 3102F10600 User Manual( Revision 1.0)Copyright O2015 Allwinner Technology. Co, Ltd. All Rights ReservedPage 10
- 2020-11-28下载
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北斗三号新体制多功能可配置双通道采样器SIS800
北斗三号新体制多功能可配置双通道采样器SIS800,可支持卫星导航全频点系统频段中频数据采集,基于USB3.0接口上传数据目录第一部分北斗三号新体制多功能可配置双通道采样器SS800-硬件连接说明北斗三号新体制多功能可配置双通道采样器S|S800参数说明二.北斗三号新体制多功能可配置双通道采样器S|s800前后面板介绍三.北斗三号新体制多功能可配置双通道采样器S|S800上电使用说明第二部分北斗三号新体制多功能可配置双通道采样器S|s800USB30驱动程序安装说明…10第三部分北斗三号新体制多功能可配置双通道采样器S|S800-上位机软件安装及使用说明….16上位机软件安装说明…16第四部分基于 Matlab卫星中频信号捕获软件使用说明22采样数据组织格式.22二. Matlab程序使用说明.23第一部分北斗三号新体制多功能可配置双通道采样器S|S800-硬件连接说明北斗三号新体制多功能可配置双通道样器S|S800是上海宇志通信技术有限公司在2018年最新推出的一款支持多卫星导航系统频段的双通道卫星中频信号采样器,数据传输采用USB3.0接口,20MHz/0.01ppm恒温晶振做为设备的同步参考时钟。双通道采样器中的每个通道可灵活配置采集的频段(1.0GHz~20GHz即L波段范围)、带宽(2046MHz~32736MHz,步进2.046MHz,其中32736MHz的带宽支持北斗号新体制信号B1C的系统带宽),两个通道联动设置采样频率(10MHz、20MHz、40MHz)以及数据位宽(4比特、8比特)在使用这款卫星中频信号采样的过程中,需特别提请用户注意的是,S|S800内部采用恒温晶振来做为设备的同步参考晶振,而恒温晶振通常需要有一个预热的过程,因此建议用户预热3~5分钟,即开机3~5分钟后进行样工作。北斗三号新体制多功能可配置双通道采样器S|S800参数说明(1)主要用途卫星导航定位系统软件接收机设计开发姿态测量卫星导航定位系统芯片和接收机设计开发冫卫星导航定位接收机干扰、抗干扰研究导航卫星信号载波相位研究与应用研究导航卫星信号多径下扰研究导航卫星信号分析≯高灵敏度玊星导航接收机搜索与跟踪算法硏究高精度卫星导航接收机算法研究(2)参数设置界面北斗三号新体制多功能可配置双通道平样器-Ss800射频来样通道A参数设置射蜮采样通追B参数设置世使能]来样>使能[函道使能]射频采样通道B使胎[频选择]旧户动频勾段选择]用户手动设置射频参效扎三号B1C频射频载频率176MH(可设范围1.0~2.0GH斗三号B3I频段[信号带宽]八二号B2頻段信号带贸]信号戏边带16+2045NH可设范围116)扌斗是B3频段∈PsL1频段[样速率]PsL2频x-〉[乐样速家]平样速平->4MH(〔频通道与联动设置:EpsL5掀段优岡F1频数据位!时E53频段x=助位究]热提肉4比持〔频函与联动设置)什BE5b频CLONA5L频段初始化操怍区1单击览按钮选择存储文件路径和名(买际生成文件名会在这个文件名基砒上添加厂采样多数「间等泪关辅助信息存储文件名测览2输入仔时间卡度单位:秒)为Q时表示不限时保仔数提3单击保存数据拉钮"开始保存从UB30妄妾收到的数据保存数据4)上位进度0000秒(3)技术指标:●推荐天线基本指标:极化 Polarization:右旋圆极化RHCP天线增益Gain(GBi仰角90度:≥6仰角20度≥0仰角10度:轴比:仰角90度≤3仰角15度≤5相位中心误差(mm):2LNA增益Gain(dBi)40±2驻波比∨SW.R
- 2021-05-06下载
- 积分:1