java实现excel批量导入数据到数据库（mysql）

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osg天空盒源代码，调试通过，顺利运行，对初学osg的初学者来说很有帮助。

设计一个2DPSK数字调制系统，要求：（1）设计出规定的数字通信系统的结构； （2）根据通信原理，设计出各个模块的参数（例如码速率，滤波器的截止频率等）； （3）用Matlab或SystemView 实现该数字通信系统； （4）观察仿真并进行波形分析； （5）系统的性能评价。

线性调频（LFM）脉冲压缩雷达仿真.脉冲压缩雷达能同时提高雷达的作用距离和距离分辨率。这种体制采用宽脉冲发射以提高发射的平均功率，保证足够大的作用距离；而接受时采用相应的脉冲压缩算法获得窄脉冲，以提高距离分辨率，较好的解决雷达作用距离与距离分辨率之间的矛盾。脉冲压缩雷达最常见的调制信号是线性调频（Linear Frequency Modulation）信号,接收时采用匹配滤波器（Matched Filter）压缩脉冲。

Axure RP Pro是美国Axure Software Solution 公司的旗舰产品，是一个快速的原型工具，主要是针对负责定义需求、定义规格、设计功能、设计界面的专家，包括用户体验设计师（UX） 、交互设计师（UI）、业务分析师（BA） 、信息架构师（IA） 、可用性专家（UE）和产品经理（PM） 。 本资料为Axure的中文使用手册。

关于运动模糊图像的一些分析，求点扩散函数的两个参数

参照汽车理论书上的二自由度车辆模型公式，在simulink里搭建模型，简洁明了，对初学者有一定的参考价值。

此文件为Marvell的Phy 88E1116R芯片的数据手册，文件中附有Xilinx Zynq 中对88E1116R的寄存器配置过程的详细说明，欢迎下载。说明:文档不是很清楚，将就着用吧

（jsp+sql）学生成绩管理系统源代码+设计报告 齐全

The Verilog® Hardware Description Language (Verilog HDL) became an IEEE standard in 1995 as IEEEStd 1364-1995. It was designed to be simple, intuitive, and effective at multiple levels of abstraction in astandard textual format for a variety of design tools, including verification simulation, timiThe clear directive from the users for these three task forces was to start by solving some of the followingproblemsConsolidate existing IeeE Std 1364-1995Verilog generate statementMulti-dimensional arraysEnhanced Verilog file i/oRe-entrant tasksStandardize Verilog configurationsEnhance timing representationEnhance the vpi routinesAchievementsOver a period of four years the 1364 Verilog Standards Group(vsg) has produced five drafts of the lrmThe three task forces went through the EEe Std 1364-1995 lRM very thoroughly and in the process of consolidating the existing Lrm have been able to provide nearly three hundred clarifications and errata for theBehavioral, ASIC, and PLI sections. In addition, the vsg has also been able to agree on all the enhance-ments that were requested (including the ones stated above)Three new sections have been added. Clause 13, "Configuring the contents of a design, deals with configuration management and has been added to facilitate both the sharing of verilog designs between designersand/or design groups and the repeatability of the exact contents of a given simulation session Clause 15Timing checks, "has been broken out of Clause 17, "System tasks and functions, "and details more fullhow timing checks are used in specify blocks. Clause 16, "Backannotation using the Standard Delay Format(SDF), addresses using back annotation(IEEE Std 1497-1999)within IEEE Std 1364-2001Extreme care has been taken to enhance the vpi routines to handle all the enhancements in the behavioraland other areas of the lrm. minimum work has been done on the pli routines and most of the work hasbeen concentrated on the vpi routines. Some of the enhancements in the vpi are the save and restart simu-lation control, work area access, error handling, assign/deassign and support for array of instances, generateand file 1/0Work on this standard would not have been possible without funding from the cas society of the ieee andOpen verilog InternationalThe IEEE Std 1364-2001 Verilog standards Group organizationMany individuals from many different organizations participated directly or indirectly in the standardizationprocess. The main body of the Ieee Std 1364-2001 working group is located in the United States, with asubgroup in Japan (EIAJ/1364HDL)The members of the IEEE Std 1364-2001 working group had voting privileges and all motions had to beapproved by this group to be implemented the three task forces focused on their specific areas and theirrecommendations were eventually voted on by the Ieee Std 1364-2001 working group