java实现excel批量导入数据到数据库（mysql）

自己做的课程设计，打包上传，电机pid调速带仿真,

上海交通大学Python课件ppt。我们自己上课的PPT，帮助还是挺大的，现在不记得的地方翻来查看查看就行了

精品PPT炼成记,小陆老师在首届锐普PPT跨界见面会上的讲义

西安电子科技大学软件工程毕业设计2019级学长的毕业设计资料大全包含代码，周报，答辩，论文等

利用stm32f103+OLED12864+FFT制作的一款音乐频谱，观赏性好，制作简单。

核主成分分析法matlab源代码，非常好的一个例子

The F1C600 processor represents Allwinner’s latest achievement in mobile applications processors. The processor targets the needs of boombox markets. F1C600 processor is based on the ARM9 CPU architecture with a high degree of functional integration. F1C600 supports Full HD video playback, iAllwinnerTechnologyRevision HistoryRevision historyVersionateDescriptionV1.0NoV10,2015nitia|Re|ease∨ersⅰonF10600 User Manual( Revision 1.0)Copyright O2015 Allwinner Technology. Co, Ltd. All Rights ReservedPage 3AllwinnerTechnologyRevision HistoryTable of contentsDeclaration2Revision histeD。着,着垂Table of contents.:::::.:::::1:4Chapter 1.About This Documentation361.1 Documentation overview36Chapter 2 Overview....372.1 Processor features2.1.1, CPU Architecture2.2. Memory Subsystem....................382.2.1. Boot rom382.2.2 SDRAM382.2.3. SD/MMC Interface..:::··:·.:::::..:·.:::::::::::··:382.3. System Peripheral.382.3.1. Timer.382.3.2.|NT392.3.3.CCU392.3.4.DMA,392.3.5.PWM,392.4. Display subsystem39241. Display engine…,,…...:::::392.4.2. Display output.....39F10600 User Manual( Revision 1.0)Copyright O2015 Allwinner Technology. Co, Ltd. All Rights ReservecPage 4AllwinnerTechnologyRevision History2.5. Video Engine26.| mage Subsystem…D看看1,翻看、·着国,着,,,面面,2.6.1.CS|4看402.6. 2 CVBS Input402. 7. Audio Subsystem2.7.1, Audio codec2.8. System Peripherals2.8.1.USB2.00TG412.8.2. KEYADC412.8.3.Tl:::::412.8.4. Digital Audio Interface.....................2.8.5.UART412.8.6.SP412.8.7.TW|422.8.8.CIR422.8.9,RSB422.8.10.OWA.422.9 Package422.10. System block Diagram43Chapter3. System..........................,443.1. Memory Mapping….453.2. CCU2463.21 Overy3.2.2, FeatureF10600 User Manual( Revision 1.0)Copyright O2015 Allwinner Technology. Co, Ltd. All Rights ReservecPage 5AllwinnerTechnologyRevision History3.2.3. Functionalities Description3.23.1. System bus….:.:::..a...:::::::非3.23.2 Bus clock tree473.2.4. CCU Register List…….473.2.5. CCU Register Description483.2.5. 1 PLL CPU Control Register3.2.5.2. PLL AUDIO Control register......................493.2.5.3. PLL VIDEO Control Register503.2.5.4. PLL VE Control Register513.2.5.5. PLL DDR Control Register3.2.5.6. PLL PERIPH Control Register...............523.2.5.7. CPU Clock Source register533.2.5.8. AHB/APB/HCLKC Configuration Register543.2.5.9. Bus Clock Gating Register O.......553.2.5. 10. Bus Clock Gating Register 1................553. 2.5.11. Bus Clock Gating Register 2563.2.5.12. SDMMCO Clock Register583.2.5.13. SDMMCl Clock Register.58325.14. DAUDIO Clock Register……593.2.5.15. OWA Clock Register.........................593.2.5.16. CIR Clock Register.603.2.5.17. USBPHY Clock Register603.2.5. 18 DRAM Gating register.603.2.5. 19 BE Clock Register61F10600 User Manual( Revision 1.0)Copyright O2015 Allwinner Technology. Co, Ltd. All Rights ReservecPage 6AllwinnerTechnologyRevision History3.2.5.20. FE Clock Register623. 2.5.21. TCON Clock Register623.2.5.22. De-interlacer Clock Register623.2.5.23. TVE Clock Register∴633.25.24. TVD Clock Register……643.2.5.25. CSI Clock Register643.2.5.26. VE Clock Register.......653.2.5.27. AUDIO CODEC Clock Register653.2.5.28. AVS Clock Register.653.2.5.29. PLL Stable Time register 0653.2.5.30. PLL Stable Time Register 1...............................................................653.2.5.31. PLL CPU Bias register663.2.5.32. PLL AUDIO Bias Register663.2.5.33. PLL VIDEO Bias Register663.2.5. 34 PLL VE Bias Register673.2.5.35.PLL_ DDR Bias Register…..,…,…,…673.2.5.36.PLL_PER| PH Bias Register……673.2.537.PLL_ CPU Tuning Register.……683.2.5.38. PLL DDR Tuning Register683.2.5.39. PLL AUDIO Pattern Control register........................693.2.5.40. PLL VIDEO Pattern Control Register.693.2.5. 41. PLL DDR Pattern Control Register3.2.5.42. Bus Software Reset Register O..3.2.5.43. Bus Software Reset register 1F10600 User Manual( Revision 1.0)Copyright O2015 Allwinner Technology. Co, Ltd. All Rights ReservecPage 7AllwinnerTechnologyRevision History3.2.5.44. Bus Software Reset Register 23.2.6. Programming guidelines3.2.6.1.PLL4看3.2.6.2.BUS3.3. Timer743.3 1. Overvi翻着看743.3.2, Feature…743.3.3. Functionalities Description..743.3.3.1. Typical Applications743.3.3.2. Functional block Diagram753.3.4.Timer Register List.......................753.3.5. Timer Register Description3.3.5.1. Timer IRQ Enable Register...763.3.5.2. Timer iRQ Status Register3.3.5.3. Timer 0 Control Register3.3.5.4. Timer o Interval value register .................................3.3.5.5. Timer 0 Current Value Register3.3.5.6. Timer 1 Control Register....3.3.5.7. Timer 1 Interval value register,7933.58. Timer1 Current Value Register…....…793.3.5.9. T imer 2 Control register3.3.5.10. Timer 2 Interval value Register803.3.5. 11 Timer 2 Current Value register3.3.5. 12 AVS Counter Control Register81F10600 User Manual( Revision 1.0)Copyright O2015 Allwinner Technology. Co, Ltd. All Rights ReservedPage 8AllwinnerTechnologyRevision History3.3.5.13. AVS Counter O Register.81335.14. AyS Counter1 Register.,,…,;…,…,…,…813.3.5.15. AVS Counter Divisor Register….,.,,,,…,,…3.3.5.16. Watchdog irQ Enable Register.………823.3.5.17. Watchdog statusster823.3.5.18. Watchdog Control Register83335.19. Watchdog Configuration Register……,,,…833.3.5.20. Watchdog Mode register....833.3.6. Programming Guidelines843.3.6.1. Timer,,84336.2. Watchdog….…843. 4, PWM853.4.1. Overview853.4.2 Feature853.4.3. Functionalities Description853. 1. Functional Block Diagram......着,着面853.4.4. Operation Principle863. 4.4.1. PWM output pins863.4.5. PWM Register List……3.4.6. PWM Register Description.....................3.4.6.1. PWM Control Register.3.4.6.2. PWM Channel 0 Period Register883.4.6.3. PWM Channel 1 Period register893.5.NTC.90F10600 User Manual( Revision 1.0)Copyright O2015 Allwinner Technology. Co, Ltd. All Rights ReservedPage 9AllwinnerTechnologyRevision History3.5.1. Overview903.5.2, Feature.:..:.:::::a:::.:::.:.a..:::::.:::::903.5.3. Functionalities Description903.5.3.1. Functional Block Diagram903.5.4.Interrupt source913.5.5. INTC Register List.....................................3.5.6. INTC Register Description…923.5.6.1. Interrupt Vector Register.……923.5.6.2. Interrupt base Address register933.5.6.3. NMI Interrupt Control Register933.5.6.4. Interrupt irQ Pending register o933.5.6.5. Interrupt iRQ Pending register 1...............933.5.6.6. Interrupt Enable register o933.5.6.7. Interrupt Enable Register 1.............933.5.6.8. Interrupt Mask register 0943.5.6.9. Interrupt Mask Register 1.::::943.5.6.10. Interrupt Response Register O.......943.5.6.11. Interrupt Response Register 1943.5.6.12. Interrupt Fast Forcing register 0943.5.6.13. Interrupt Fast Forcing Register 1....................................................................953.5.6. 14 Interrupt Source Priority Register O953.5.6.15. Interrupt Source Priority Register 1...973.5.6.16. Interrupt Source priority register 21003.5.6. 17 Interrupt source priority register 3102F10600 User Manual( Revision 1.0)Copyright O2015 Allwinner Technology. Co, Ltd. All Rights ReservedPage 10

EMD经验模式分解工具箱，EMD经验模式分解工具箱，EMD经验模式分解工具箱。

目标识别是计算机视觉一个重要的研究领域，由此延伸出的车辆型号识别具有重要的实际应用价值，特别是在当今交通状况复杂的大城市，智能交通系统成为发展趋势，这离不开对车辆型号进行识别和分类的工作，本文围绕如何利用计算机视觉的方法进行车辆型号的识别和分类展开了一系列研究：本文对当前的目标识别和分类的特征和算法做了总结和归纳。分析比较了作为图像特征描述常见的特征算子，总结归纳了他们的提取方法、特征性能以及相互之间的关联。另外，介绍了在目标识别工作中常用的分类方法,阐述了他们各自的原理和工作方法。研究了深度神经网络的理论依据，分析比较了深度神经网络不同的特征学习方法，以及卷积

自己写了一些注释，主要是刚开始还不是很熟悉Simulink里的一下模块，然后其中的机理就不太清楚，所以加了一些注释在里面