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OFDMA System Analysis and Design

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OFDMA系统分析与设计的国外经典教材Chapter 1 Introduction to OFDM and OFDMAChapter 2 Characterization of the Mobile Wireless ChannelChapter 3 Fundamentals of Digital Communications and NetworkingChapter 4 Fundamentals of OFDM and OFDMA: Transceiver StructureChapter 5 Physical Layer: Time and FrequencyChapter For a listing of recent titles in theArtech House Mobile Communications Library,turn to the back of this bookOFDMA System Analysis and DesignSamuel C. YangARTECHHOUSEBOSTON LONDONartechhouse. comLibrary of Congress Cataloging-in-Publication DataA catalog record for this book is available from the U.S. Library of CongressBritish Library cataloguing in Publication DataA catalogue record for this book is available from the british libraryISBN-13:978-1-60807-076-3Cover design by vicki KaneC 2010 Artech House685 Canton streetNorwood. MA 02062All rights reserved. Printed and bound in the United States of America. No partof this book may be reproduced or utilized in any form or by any means, elec-tronic or mechanical, including photocopying, recording, or by any informationstorage and retrieval system, without permission in writing from the publisherAll terms mentioned in this book that are known to be trademarks or servicemarks have been appropriately capitalized artech House cannot attest to theaccuracy of this information. Use of a term in this book should not be regardedas affecting the validity of any trademark or service mark10987654321To my beautiful wife JennyContentsPrefaceAcknowledgmentsXVCHAPTER TIntroduction to ofdm and ofdma1.1 Motivation1.2 Conventional FDm1.3 Advantages of FDm1.3.1 Intersymbol Interference(ISI)and Multipath Fading1.3.2 Modulation and Coding per Subcarrier1.3.3 Simple equalization1.4 Disadvantages of FDM1.5 Basics of ofdm1.6 Advantages of OFDM1.6.1 Low-Complexity modulation1.6.2 Spectral Efficiency1.7 Basics of ofdma1.8 Advantages of OFDMA121.9 Some Practical issues of ofdm and ofdma1.9.1 Time Domain: Interblock Interference131.9.2 Frequency Domain: Intercarrier Interference131.10 OFDM and Dsss141.11 Overview of the book14References15Selected BibliographyCHAPTER 2Characterization of the mobile wireless channel2.1 Introduction2.2 Link analysis2.3 Distance Dimension: Propagation Loss2.3.1 Path Loss2.3.2 Shadowing Loss24Contents2.3.3 Multipath Fading26Example 2.1282.3.4 Concluding Remarks292.4 Time Dimension: Multipath Delay Spread302.4.1 Delay Spread30Example 2.231Example 2.3312. 4.2 Coherence bandwidth322.4.3 Implications for OFDM352.5 Frequency Dimension: Doppler Spread362.5.1 Doppler Spread36Example 2. 4372.5.2 Coherence time2.5.3 Implications for OFDM402. 6 Conclusions41References43Selected Bibliography44ChAPTER 3Fundamentals of Digital Communications and Networking453.1 Introduction453.2 Basic Functions of a Transceiver453.3 Channel Coding473.3.1 Linear block codes473.3.2 Convolutional codes493.4 Symbol mapping and modulation3.5 Demodulation563. 5. 1 Matched Filter563.5.2 Symbol Error3.6 Adaptive Modulation and Coding603.7 Cyclic Redundancy Check(CRC)623.8 Automatic Repeat Request(arQ)643.8.1 Stop-and-Wait ARQ643.8.2 Sliding Window arQ653.9 Hybrid ARQ67References69Selected bibliographyCHAPTER 4Fundamentals of ofdm and ofdma: transceiver structure4.1 Basic Transmitter functions714.2 Time domain: guard time4.3 Frequency Domain: Synchronization744.4 Basic receiver functions754.5 Equalization764.6 OFDM Symbol79Contents4.7 OFDMA Transmitter844. 8 OFDMA Receiver4.9 OFDMA4.9.1 Frequency diversity4.9.2 Multiuser diversity914.9.3 Concluding Remarks4.10 Peak-to-Average Power ratio924.11 Conclusions93References94Selected Bibliography95CHAPTER 5Physical Layer: Time and Frequency975.1 Introduction5.2 Distributed Subcarrier Permutation: Forming Subchannels onDownlink5.2.1 Full Usage of Subchannels(FUSC1005.2.2 Partial Usage of Subchannels(PUSC)1015.2.3 Tile Usage of Subchannels 1(TUSC1)1025.2.4 Tile Usage of Subchannels 2(TUSC2)1025.3 Distributed Subcarrier Permutation: Forming Subchannels on Uplink 1025.3.1 Partial Usage of Subchannels(PUSC)1035.3.2 Optional Partial Usage of Subchannels(Optional PUSC)1035.4 Adjacent Subcarrier Permutation: Downlink and Uplink1045.5 Summary of Subcarrier Permutation Modes1045.6 Bursts and Permutation Zones1055.7 Subframes and frames1075.7.1 Preamble1105.7.2 Frame Control Header(FCH)1105.7.3 Downlink MAP (DL-MAP)and Uplink MAP(UL-MAP1115. 8 TDD and FDD5. 9 System Design Issues1125.9.1 Frequency Diversity and multiuser diversity1125.9.2 Segmentation1125. 10 Adaptive burst profiles1155.10.1 Burst Profiles1155.10.2 Channel Quality Feedback116References117ChAPTER 6Physical Layer: Spatial Techniques1196.1 Introduction6.2 Spatial Diversity: Receive Diversity1206.2.1 Receive Diversity: Antenna Selection1226.2.2 Receive Diversity: Maximal Ratio Combining6.3 Spatial Diversity: Transmit Diversity123Contents6.3. 1 Transmit Diversity: Open-Loop 2 X 11246.3.2 Transmit Diversity: Open-Loop 2X 21266.3.3 Transmit Diversity: Closed-Loop Antenna Selection128Example 6.11296.3.4 Transmit Diversity: Closed-Loop precoding1306.3.5 Remarks1326.4 Spatial Multiplexing1336.5 MIMO-OFDM1366.6 Beamforming1366.7 System Design Issues139References140Selected Bibliography141CHAPTER 7Medium Access control: architecture and data plane1437.1 MAC Architecture1437.2 Convergence Sublayer1457. 2.1 Address Mapping( Classification1467. 2.2 Header Suppression1467. 3 Common Part Sublayer1477.3.1ARQ1477. 3.2 MAC SDU and MAc pdu1487.3.3 Fragmentation/Packing1497.4 Security Sublayer152References152chaPTeR 8Medium Access Control Lower Control plane1538. 1 Introduction1538.2 Scheduler1538.3 Bandwidth Request1558.3.1 Request in Existing Uplink Allocation1568.3.2 Unicast Polling1568.3.3 Multicast and Broadcast Polling1578.3.4 Contention-Based Request for OFDMA1578.4 Control Signaling1588.5 Ranging1598.5.1 Initial Ranging1598.5.2 Periodic Ranging1608.5.3 Handover ranging1618.6 Power Control1618.6.1 Uplink Power Control: Closed-Loop1648.6.2 Uplink Power Control: Open-Loop1668.6.3 Assignment of Uplink Modulation and Coding8.6.4 Concluding Remarks168References169ContentsChaPTER 9Medium Access Control: Upper Control plane1719.1 Introduction1719.2 Network Entry1719.2. 1 Synchronization with Downlink of Base Station and acquisitionof parameters1739.2.2 Initial Ranging1739. 2.3 Negotiation of Mobile Capabilities1749.2.4 Security Procedures1749.2.5 Mobile registration1759.2.6 IP Connectivity1759.2.7 Connection Setup1769.3 Mobility Management: Link Handover1769.3.1 Cell Reselection1779.3.2 Hard Handover(HHO1799.3.3 Macro Diversity Handover(MDHO)1849.3.4 Fast Base Station Switching(FBSS1879.3.5 System Design Issue: H Add and h delete1899.3.6 Concluding Remarks1919.4 Mobility management: Network handover192References192CHAPTER 10Quality of Service(Qos)19510.1 Introduction19510.2 Definitions and Fundamental Concepts19510.2.1 Service Flows and Qos Parameters19510.2.2 Connections19610.3 Object Relationship Model19710.4 Service flow transactions19910.4.1 Creating a Service Flow19910.4.2 Changing a Service Flow20010.4.3 Deleting a Service Flow20310.5 QoS Parameters20410.6 Scheduling Services20610.6.1 Unsolicited Grant Service(UGS)20610.6.2 Real-Time Polling Service(rtPS20710.6.3 Extended Real-Time Polling Service(ertPS20710.6.4 Nonreal-Time Polling Service(nrtPS20810.6.5 Best Effort(BE)20810.6.6 Remarks209References210

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Nov 201夲部分讲解如何配置芯片上的嵌套向量中断控制器。完整信息清参阅htp/www.arm.com。InterruptsModulePPBNested VectoredModuleInterrupt Controller(NVIC)Module图32嵌套向量中断控制器题日相关模块参考链接套问量中断控制器http://www.arm.com系统内存映System memory map时钟Clock distribution电源管理Power management专用外设总线ARM Cortex-M4核心 ARM Cortex-M43.22.1中断优先级器件支持16级中断优先级,因此在嵌套向量中断控制器中,每一个中断源在优先级控制寄存器IP中都有4个位。例如IPRO中3302928a7262524232221a019181716|151413121110976543210R0000006000600000W3.22.2非可屏蔽中断非可屏蔽中断的中断源来自于外部的NM引脚。此引脚是多路复用引脚,必须要配置他的功能,使其成为外部不可屏蔽中断功能引脚。322.3中断分配中断默认按照下表分配向量号:当中断使用时,此值储存在栈中。IRQ号:非核心中断源,对应的编号为终端号减16。IRQ号在ARM的NVC文档中有描述表34中断号分配址址中断编号IRQ号非优先级编中断伏先溟模块描述(1)号(2)级编号(3)ARM核心中析源0x00000000ARM内核切始牟栈指针0x00000004ARM内核初始程序计数器Editbylie:soonli@qq.comK60P144M100SF2RM. pdfK60 Sub-Family Reference Manual, Rev. 6 NoV 2010x00000082AHM内核非可屏蔽中断x00000c3ARM内核哽件故障0x000000101ARM内核存储控制器故障0x0000145ARM内核总线故障0x000000186ARM内核用故障0x000001C70x00002080x0000219x00028100x000002C11ARM内核管理程序调入0x000003012ARM内核周试监控0x000034130x0000003814ARM内核0x0000315ARM内核系统往拍定时器非核心中新源0x00000040160DMADA通道0发送完成0x000000141DMADMA通道⊥发送完成0×00004818DMAD)MA通道2发送完成000401DMA通道3发送完成0x0000020DA通道4发送完成0300052DMA通道5发送完成0x00000582DMADMA通道6发送完成0x000_005C2sDMADMA通道7发送完成0x0000006021DMA通道8发送完成0x0000006425DMADMA通道9发送完成0x0000006826⊥0DMADMA通道10发送完成0x000006C27DMADMA通道11发送完成0x00007028DMA通道12发送完成0x000007429DMA通道13发送完成0x0000087314DMA通道1发送完成0x00007C3IMA通道15发送完成0x00000803216DMADMA通道0-15故障0x00000081MCM0x00000883184闪存命令执行完成0x000008C35闪存读取冲突0x0000009036模式控制掉电中断,电检测低澌喚醒单兀注意:在需要使用低漏检测0x00000094370低漏唤醒|的时候不要禁止这个中断0x000009838看门狗看门狗中断0x0000009c39230x00000A441IICIEditbylie:soonli@qq.com4K60P144M100SF2RM. pdfK60 Sub-Family Reference Manual, Rev. 6 NoV 2010x0000A84SPD所有中断源使用一个向量x0000AC4SPI1所有中断源使用一个向量0x000000B014SPI2所有中断源使用一个向量CR’ ed Message bufi0x000000B44529CANO(0-15)0x00000846CAND总线关闭0x0000BC47错误0x000000C048CANO发送报警x00000C449CANO接收报整0x000000C850CAND唤帼0x00000CC50x0000000520x000000D1537CAN⊥5)0x000000D8CANI总线关闭0x00000DC5CAN⊥错误0x000000E05610发送报警0x0000C457接收报警0x0000E858唤醒0x0000EC59100x0000F06011l⊥0000F461JJARTO串口0状态中新源0x00000F862UARTO串口0错误中新源0y000000FC11UARTI串口1状态中断源0x00010064UARTI串口1错昃中源x0000010465UART2串口2状态中新源000001085650UART2串口2错昃中粉溴0x000067UaRT串口3状态中新源0x000011068UART串口3错误中析源0x0001146gUART4串口4状态中析源00011870UART串口4错误中析源0x0000011C715513UART串口5状态中新源0x0000120721111111UART5串5错误中析源0x00001247370x000128740x00012c75CMPO0x00003076CMPI0x000013476115CMP20x000001387815FTM0所有中断源使一个向量0x000013C7963FTM1所有中断源使用一个向量0x00001408064FTM2所有中断源使用一个向量000014481160x0000014816报警中断Editbylie:soonli@qq.comK60P144M100SF2RM. pdfK60 Sub-Family Reference Manual, Rev. 6 NoV 2010x00014C8x0001508PITPIT通道00x000001518517PITPIT通道10x0000015886017PITPIT通道20x0000015C81PITPIT通道30x0000160882180x000016489USB OTx001689074充电检测0x0000016C|91Ethernet macIEEE1588定时器中断0x000017092Ethernet mac发送中断0x0000017497719Ethernet mac接收中断0x00001789EtherneL mac错误和其他中断0x00017C950x00000180|96SDH0x00184978120DACO0x000001889DACI0x0001899TsT所有中断源使用一个向量0x0000901008120x0000194101低功耗定时器00001981020x000019c10321引因控制模块PORTA引脚中断000001A0104引却控制模块PORTB引脚中断00004105引脚控制模块PORTC引脚中断0x0001AB106引閎控制模块PORTD引脚中断0x00000⊥AC10791引脚控制模块P0RTE引脚中断0×001B01080x000011090×00010701094软中断软件中断(4)(1)表示嵌套向量中断控制器的中断源号(2)表示嵌套向量中断控制器对于响应中断的ISER,ⅠCER,ISPR,ICPR和IABR寄存器的值,计算方法是IRQ的值除以32。(3〕表示嵌套向量中断控制器对于响应中断的IPR寄存器的值,计算方法是IRQ的值狳以4(4)此中断只能被NVC寄存器置位或者清零。3.2.2.3.1确定位域和寄存器的位置,来配置一个特定的中断如果你需要配置低功耗寄存器中断,下面的表格自“中断号分配”地址中断编号1RQ号非优先级编中断优先源模块描述号(2)级编号(3)0x0000019410」2⊥低功耗定时器译者注:下面角标的注解没有被列出,请看上表末尾。1)在NⅥC寄存器中,你需要配置关于中断的信息Editbylie:soonli@qq.comK60P144M100SF2RM. pdfK60 Sub-Family Reference Manual, Rev. 6 NoV 201· NVICISER2NVICICER2· NVICISPR2· NVICICPE2NVICIABR2NVICIPR212)确定特定中淅在相对应的寄存器中的特定位域(汗,这句话怎么这么别扭)。NVICISER2, NVICICER2, NVICISPR2, NVICICPR2, NVICIABR2 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