14级软件工程专业本科优秀毕业设计（论文）——基于Android的个人理财软件的设计与实现 管理资料（开题报告，任务书，进度计划，实习报告，文献翻译等）

SLIC的matlab代码，可以更改自己的图片位置，生成结果，可以直接运行使用

机载下视圆周SAR三维BP成像，对学习CSAR成像算法的同学很有帮助庞守宝,等:机载下视圆周SAR三维BP成像匚发射信号]一世P点救射回波信号时间匹配滤波补偿相位因子DBP成像相十叠加0)0图5同一高度x平面内4点的能量图成像显示图3算法的成像流程图103仿真结果60仿真的场景是在三维平面上立方体的8个顶点,场景的原始三维仿真图如图4所示。仿真中的主要的303035系统参数如表1所示。表1仿真所用的主要系统参数10载波波长0.008m带宽750 MHz脉冲重复频率飞行高度0203040506070801000m/n角速度0.4rads载机飞行半径100m阵元数目阵元间距0.008m图6同一高度x平面内4点的等高线dB图10108口424044维/363436-10-6y/m原始场景图7BP成像之后的初始结果图图4原始场景图系统仿真的结果如图5~图8所示。图5为同高度4点的能量图,从图5中可以看出,有目标的区域能量积聚非常明显,没有目标的区域能量很小,几乎可以忽略,这正是BP算法相干累积的优点。图65为同一高度4点的等高线图,从图中可以得知,点目rim标存在处的能量较为集中,有目标的区域相对没有目y/m场景恢复标的区域的dB差较大,能量差异通过右边的色彩进度条来表示。图7为截取某一门限后BP成像的结果图8场景恢复之后的成像图图,根据图中8点位置可知,BP累积之后的初始成像4结束语相对于原始场景只是出现了坐标的平移,8个点的相对位置是正确的。图8为BP成像结果转换到原坐标分析了飞机圆周飞行时对地面场景目标的三维成系之后的成像结果。比较图4和图8,可以得知,圆像结构和成像机理,机载下视三维圆周SAR区别于周SAR三维BP成像的结果和原始场景吻合,即圆周普通的直线飞行的三维SAR在于回波信号距离压缩SAR可以精确的还原目标场景的三维信息。之后出现沿航向和切航向的耦合项,使得经典的RD16庞守宝,等:机载下视圆周SAR三维BP成像电炮是算法、CS算法和距离徙动算法等受限,BP算法通过(8):1252-1265二维搜索,避免了单独处理每一维的过程,之后通过[5] Wang Y P, Tan WX, Hong W,etal. Focusing Bistatic像素单元离散化、补偿每一距离门相位因子、相干累Circular SAR Data Using Polar Format Algorithm [C]. Syn-积等步骤构建场景目标函数,完成成像处理。三维场thetic Aperture Radar, APSAR2009, 2 Asian -PacificConferences on digital Objects Identifier, 2009: 989景仿真结果表明,圆周SAR能够精确的还原场景目992.标的三维信息。此结构在地质斯探和自然灾害救援等[6]Du Lei, Wang Yanping, Honf Wen, et al. Analytic Mod-有现实意义。eling and Three Dimensional Imaging of Downward- Loo-参考文献king Sar Using Bistatic Uniform Linear Array Antenna[C]. Ist Asian and Pacific Conference on Synthetic aper-[1] Hong W, Wang Y P, Tan WX, et al. Tomographic SARture Radar Proceedings, 2007: 49-53and Circular SAR Experiments in Anechoic Chamber [c]. [7] Jens Klare, Matthias Wei, Olaf Peters, et al. ARTINOGermany: EUSAR, 2008A New High Resolution 3D Imaging Radarsystem on an Au-[2] Cantalloube H, Colin E. Airbome SAR Imaging Along a Cirtonomous Airborne Platform [C]. Greeces: IGARSScular Trajectory [c]. Germany EUSAR, 2006: 16-182006:3842-3845[3] Riot H. Cantalloube, Circular SAR Imagery for Urban Re- [8] Wei M, Ender J, Peters 0, et al. An Air-bone Radarmote Sensing [c]. Germany: EUSAR, 2008: 2-5for Three Dimensional Imaging and Observation - Technical[4] Soumekh M. Reconnaissance with Slant Circular SAR ImaRealisation and Status of ARTINO [C]. Germany: EU-ging [J]. IEEE Trans. On Imaging Proccessing,1996,5SAR, Dresden,2006:5315-5318“→·“M“+“““M(上接第11页)[5]施韶华,李孝辉,刘阳.基于直接数字频率合成的高精参考文献度频率源设计[J].电子测量与仪器学报,2008(90):[1]周殿清.基础物理实验[M].北京:科学出版社,200385-389[2]杨刚,周群.电子系统设计与实践[M].北京:电子工[6]王军证,王建斌,陈仁伟.基于DDS的超声导波信号业出版社,2004源的设计[J.电子测量技术,2010,33(2):19-2.[3]刘海成.AVR单片机原理及测控工程应用[M].北京:[7]吴加政,苏新彦.基于DDs的信号模拟器设计J.国北京航空航天大学出版社,2008外电子测量技术,2009,28(10):67-70[4]柴媛媛,唐慧强,辛红伟.基于ARM和DS技术的信[8] ST Microelectronics Corporation,smFI03 XX Datasheet[EB/号源设计[J].通信技术,2009,42(10):54-56OL].(209-12-14)[2010-03-10]ww.st.com+一中““-(上接第13页)器的输出波形。图4所示为示波器测量仿真输出波形。真分析,在编辑电路、调整元件参数时十分方便,它可以进行各种电子电路的设计与仿真,并且仿真精度高。给电路设计测试带来方便,使电子线路的设计、性能参数的仿真等繁琐的任务变得轻而易举。参考文献[1]郑步生. Muhisim2001电路设计及仿真入门与应用[M]北京:电子工业出版社,2002.[2]张新喜. Multisim10电路仿真及应用[M].北京:机械图4示波器测量仿真输出波形工业出版社,20102结束语[3]美国国家仪器有限公司. NI Multisim1l简化教学和设计中的电路仿真[Z/OL].(2010-02-01)[2010-05-在时序逻辑电路设计中应用 Multisim软件进行仿11http://www.ipcm.com.cn机载下视圆周SAR三维B成像旧WANFANG DATA文献链接作者:庞守宝,张晓玲,吴堃, Pang Shoubao, Zhang Xiaoling, Wu Kun作者单位:电子科技大学,电子工程学院,四川,成都,610054刊名:电子科技英文刊名:ELECTRONIC SCIENCE AND TECHNOLOGY年,卷(期):2010,23(12)参考文献(8条)Wei M; Ender J; Peters 0 An Air-borne Radar for Three Dimensional Imaging and Observation-TechnicalRealisation and status of artin 20062. Jens Klare; Matthias Wei: Olaf Peters ARTINO: A New High Resolution 3D Imaging Radarsystem on anAutonomous airborne plat form 20063. Du Lei; Wang Yanping; Honf Wen Analytic Modeling and Three-Dimensional Imaging of Downward-LookingSAR USing Bistatic Uniform Linear Array Antennas 20074. Wang y P; Tan W X; Hong W Focusing Bistatic Circular SAR Data Using Polar Format Algorithm 2009oumekh M Reconnaissance with Slant Circular SAR Imaging 1996(08)6. Oriot H Cantalloube Circular SAR Imagery for Urban Remote Sensing 20087. Cantalloube H; Colin E Airborne Sar Imaging Along a Circular Trajectory 20068. Hong W; Wang y P; Tan W X Tomographic Sar and Circular Sar Experiments in Anechoic Chamber 2008本文链接http://d.g.wanfangdata.comcn/periodiCaldzkj201012005.aspx

大气压强传感器BMP280单片机程序，主控为C51单片机，包括I2C协议和串口协议，I2C与传感器通信，串口与上位机通信，串口波特率为9600，通信引脚为RXD：3.0，TXD：3.1，I2C通信引脚SCL：1.5，SDA：1.4

altera公司IP核使用手册,对于学习EDA技术的学生或工程师有用A吉RAContentsChapter 1. About this MegaCore FunctionRelease informat1-1Device Family Support···Introduction.··········FeaturesOpen core plus evaluation1-3Performance···Chapter 2. Getting StartedDesign Flow衡·鲁·,看·,音番2-1Megacore Function walkthrough2-2Create a New quartus II Pi2-2Launch the mega Wizard Plug-in ManagerStep 1: Parameterize2-5Step 2: Set Up SimulationStep 3: Generate..,2-11Simulate the design2-13Compile the design2-13Pa Device2-14Set Up Licensing2-15ppend the license to yourdat file2-15Specify the License File in the Quartus II Software...2-15Example Simulation and Compilation..2-16Example quartus Ii project2-16Example simulation with Test Vectors,,,,,,2-16Chapter 3. SpecificationsyperTransport Technology Overview1HT SyStems3-2HT Flow ControlHyper Transport MegaCore Function SpecificationPhysical InterfaceSynchronization and alignment ...Protocol interfClocking Options.......HyperTransport Mega Core Function Parameters and HT Link Performance3-10Signals3-14CSR Module...3-31OpenCore plus time-Out BehaviorAppendix A. ParametersIntroduction鲁鲁鲁A-1Parameter listsDevice Family and Read Only registers···········,,,,,,,,,,A-1Base Address Registers番鲁,A-2Clocking OptionsA-3Advanced settingso March 2009 Altera corporationHyperTransport MegaCore Function User GuideAppendix B. Stratix Device Pin AssignmentsIntroductionB-1GuidelinesAppendix C. Example designGeneral descriptionAdditional informationRevision historyInto-lHow to Contact alteraInfo-1Typographic Conventions ..........Info-2Hyper Transport MegaCore Function User Guideo March 2009 Altera CorporationA吉RA1. About this MegaCore FunctionRelease InformationTable 1-1 provides information about this release of the Hyper Transport Mega CoretfunctioTable 1-1. Hyper Transport Mega Core Function Release InformationitenlDescription∨ ersion9.0Release dateMarch 2009Ordering codeIP-HTProduct ID(s)0098Vendor iD(s)6AF7Altera verifies that the current version of the quartus@ll software compiles theprevious version of each MegaCore function. Any exceptions to this verification arereported in the Mega Core lP Library release Notes and Errata. Altera does not verifycompilation with Mega Core function versions older than one releaseDevice Family SupportMegaCore functions provide either full or preliminary support for target Alteradevice families:Full support means the Mega Core function meets all functional and timingrequirements for the device family and may be used in production designsa Preliminary support means the Mega Core function meets all functionalrequirements, but may still be undergoing timing analysis for the device family;itmay be used in production designs with cautionTable 1-2 shows the level of support offered by the Hyper Transport MegaCorefunction for each of the altera device familiesTable 1-2. Device Family SupportDevice FamilySupportHard Copy Stratix@FullStratixFulStratix IIFulStratix‖GXPreliminaryStratix GXOther device familiesNo supportC March 2009 Altera CorporationHyperT ransport Mega Core Function User Guide1-2Chapter 1: About this MegaCore FunctionIntroductionIntroductionThe Hyper Transport Mega Core function implements high-speed packet transfersbetween physical(PhY) and link-layer devices, and is fully compliant with theHyperTransport l/O Link Specification, Revision 1.03. This Mega Core function allowsdesigners to interface to a wide range of Hyper TransportTm technology(hT)enableddevices quickly and easily, including network processors, coprocessors, videochipsets, and ASICsFeaturesThe Hyper Transport Mega Core function has the following features8-bit fully integrated hT end-chain interfacePacket-based protocolDual unidirectional point-to-point linksUp to 16 Gigabits per second(Gbps)throughput(8 Gbps in each direction)200, 300, and 400 MHz DDR links in Stratix and Stratix GX devices200, 300, 400, and 500 MHz ddr links in Stratix II and Stratix II GX devicesLow-swing differential signaling with 100-Q2 differential impedanceHardware verified with Hyper fransport interfaces on multiple industry standardprocessor and bridge devicesFully parameterized mega core function allows flexible, easy configurationFully optimized for the altera stratix Il, Stratix, Stratix GX, and Stratix II GXevice famillesApplication-side interface uses the Altera AtlanticTM interface standardManages Hr flow control, optimizing performance and ease of useIndependent buffering for each HT virtual channelAutomatic handling of ht ordering rulesStalling of one virtual channel does not delay other virtual channels(subject toorderingFlexible parameterized buffer sizes, allowing customization depending onsystem requirementsUser interface has independent interfaces for the HT virtual channels, allowingindependent user logic designCyclic redundancy code(crc) generation and checking to preserve data integrityIntegrated detection and response to common HT error conditions■ CRC errorsEnd-chain errorsFully integrated HT configuration space includes all required configuration spaceregisters and HT capabilities list registersHyper Transport MegaCore Function User Guideo March 2009 Altera CorporationChapter 1: About this MegaCore FunctionPerformance32-bit and 64-bit support across all base address registers bars)automatically handles all csr space accessesVerilog HDL and VHdL simulation supportOpen Core Plus EvaluationWith the Altera free Open Core Plus evaluation feature, you can perform the followingSimulate the behavior of a mcgafunction(Altera MegaCore function or AMPPmegafunction) within your systema Verify the functionality of your design, as well as quickly and easily evaluate itssize and speedGenerate time-limited device programming files for designs that includeMegaCore functionsProgram a device and verify your design in hardwareYou only need to purchase a license for the Mega Core function when you arecompletely satisfied with its functionality and performance and want to take yourdesign to productiono For more information about Open Core Plus hardware evaluation using theHyperTransport MegaCore function, refer to"Open Core Plus Time-Out Behavior"onpage 3-40 and AN 320: Open Core Plus Evaluation of megafunctionsPerformanceThe Hyper Transport Mega Core function uses 20 differential I/O pin pairs and 2single-ended I/O pins, requiring 42 pins total. Table 1-3 through Table 1-5 showtypical performance and adaptive look-up table (alut) or logic element (LE)usagefor the HyperTransport MegaCore function in Stratix II GX, Stratix IL, Stratix, andStratix GX devices respectively, using the Quartus@ II software version 7.1Table 1-3 shows the maximum supported data rates in megabits per second(Mbps)by device family and speed gradeTable 1-3. Maximum Supported Hyper Transport Data Rates (Note 1)Speed GradeDevice Family-36Stratix ll GX devices 1000 Mbps 1000 Mbps 800 MbpsNA(2)N/A(2NA(2)Stratix devices1000 Mbps 1000 Mbps 800 Mbps N/A(2)NA(2)NA(2)Stratix devicesN/A(2N/A(2)00 Mbps 800 Mbps 600 Mbps400 MbpsFlip-Chip packagesStratix devicesNA(2)NA(2)NA(2)600 Mbps400 Mbps400 Mbps(Wire Bond packagesStratix GX devicesN/A(2) N/A(2)800 Mbps 800 Mbps 600 Mbps N/A(2)Notes to table 1-3(1)Rates are per interface bit. Multiply by eight to calculate the uni-directional data rate of an 8-bit inter face(2) Devices ot this speed grade are not ottered in this device familyC March 2009 Altera CorporationHyperTransport Mega Core Function User GuideChapter 1: About this MegaCore FunctionPerformanceTable 1-4 shows performance and device utilization for the Hyper TransportMegaCore function in Stratix II and Stratix II GX devicesTable 1-4. Hyper Transport Mega Core Function Performance in Stratix ll and Stratix ll GX DevicesParametersMemoryUserRXCombinationalHT Link InterfacePosted Non-Posted Response ClockingALUTSLogicfMAX(MHz) MAx(MHz)Buffers BuffersBuffers Option(12)Registers M4K M512 ( 3)3)Shared3.5005200120500125(4RX/TX/Ref35005200500Ref/x8Shared36005400160500>150RX/TXShared4.0006,00016150RX/TX16Shared4,1006,200500125(4)RX/TX/RefShared4.1006200500125(4Ref/TxShared4.2006400160150RX/TXNotes to table 1-4.Refer to " Clocking Options "on page 3-7 for more information about these options(2 )Other parameters(BAR configurations, etc. )vary the alut and Logic Register utilization numbers by approximately +/-200(3)Figures for -3 speed grade devices only(4) When using the Shared Rx/Tx/Ref and Shared Ref/Tx options, the user interface frequency is limited to exactly the ht frequency divided byTable 1-5 shows performance and device utilization for the Hyper TransportMegaCore function in Stratix and Stratix GX devicesTable 1-5. Hyper Transport Mega Core Function Performance in Stratix and Stratix GX DevicesUser Interface fmaxParametersUtilizationHT Link fMAX MHz)MHZ)RXRXSpeed GradePosted Non-Posted Response Clocking Option LEsM4KBuffers BuffersBuffers)(2 Blocks.5-66Shared rx/tx/ref1240010073)100734448888Shared Ref/Tx 7, 60014400400100{3)100(3)Shared rxtx7,90016400400>125>100Shared rxtx8.900125>100168Shared Rx/T×Ref9,400124004001003)100316Shared ref/ ix9.500144001003)10073)16Shared rx/x9.700400125Notes to table 1-5:(1)Refer to Clocking Options"on page 3-7 for more information about these options(2 )Other parameters( BAR configurations etc. )vary the LE utilization by approximately +/-200 LES(3 )When using the Shared Rx/Tx/ Ref and Shared Ref/Tx options, the user interface frequency is limited to exactly the hT frequency divided by fourHyper Transport MegaCore Function User GuideC March 2009 Altera CorporationA吉RA2. Getting StartedDesign FlowTo evaluate the HyperTransport Mega Core function using the Open Core Plus feature,include these steps in your design flowObtain and install the HyperTransport Mega Core functionThe HyperTransport Mega Core function is part of the MegaCore IP Library, which isdistributed with the Quartus ii software and downloadable from the altera websitewww.altera.como For system requirements and installation instructions, refer to Quartus II InstallationLicensing for Windows and Linux Workstations on the Altera website atwww.altera.com/literature/lit-qts.ispFigure 2-1 shows the directory structure after you install the HyperTransportMegaCore function, where is the installation directory. The default installationWindows is C: altera ; on Linux it islopt/alteraFigure 2-1. Directory StructureInstallation directorypContains the Altera MegaCore IP Library and third-party IP coresalteraContains the Altera MegaCore IP LibrarycommonContains shared componentshtContains the Hyper Transport Hyper Transport Megacore function files and documentationdocContains the documentation for the Hyper Transport MegaCore functionlibContains encrypted lower-level design filesexampleContains the design example for the Hyper Transport Mega Core function2. Create a custom variation of the Hyper Transport Mega Core function3. Implement the rest of your design using the design entry method of your choice4. Use the IP functional simulation model to verify the operation of your designo For more information about Ip functional simulation models, refer to the SimulatingAltera IP in Third-Party Simulation Tools chapter in volume 3 of the Quartus II Handbook5. Use the Quartus II software to compile your designC March 2009 Altera CorporationHyperT ransport Mega Core Function User Guide2-2Chapter 2: Getting StartedMega Core Function WalkthroughIg You can also generate an Open Core Plus time-limited programming file,which you can use to verify the operation of your design in hardware6. Purchase a license for the hypertransport Mega Core functionAfter you have purchased a license for the Hyper transport mega Core functionfollow these additional steps1. Set up licensing2. Generate a programming file for the Altera device(s)on your board3. Program the Altera device(s)with the completed designMegaCore Function WalkthroughThis walkthrough explains how to create a custom variation using the AlteraHyper Transport IP Toolbench and the Quartus II software, and simulate the functionusing an ip functional simulation model and the modelsim software when you arefinished generating your custom variation of the function, you can incorporate it intoⅴ our overall projectIe IP Toolbench allows you to select only legal combinations of parameters, and warnsou of any invalid configurationsIn this walkthrough you follow these stepsCreate a New Quartus II Projecta Launch the MegaWizard Plug-in Manager■Step1: Parameterizea Step 2: Set Up Simulation■Step3: Generate■ Simulate the designTo generate a wrapper file and Ip functional simulation model using default values,omit the procedure described in"Step 1: Parameterizeon page 2-5Create a New Quartus ll ProjectCreate a new Quartus II project with the New Project Wizard, which specifies theworking directory for the project, assigns the project name, and designates the nameof the top-level design entityTo create a new project, perform the following steps1. On the Windows Start menu, select Programs> Altera> Quartus II tostart the Quartus lI software. Alternatively, you can use the Quartus II Web editionsoftware2. In the Quartus II window, on the File menu, click New Project Wizard. If you didnot turn it off previously, the New Project Wizard Introduction page appears3. On the New Project Wizard Introduction page, click NextHyper Transport MegaCore Function User Guideo March 2009 Altera Corporation

【实例简介】轨道力学，MATLAB，轨道根数，高斯方法，开普勒方程，卫星轨道

ANSYS实例分析75道，ANSYS实例分析75道，ANSYS实例分析75道。

根据光伏电池数学模型所建立的simulink光伏电池仿真模块，可设定光照强度、短路电流、开路电压、最大功率点电流与电压等参数。光伏阵列的仿真模块，只需修改相应的短路电流、开路电压、最大功率点电流与电压数值即可。

基于MATLB GUI的信号发生器可以产生正弦波、方波、指数信号及任意表达式的信号，可以设定指定信号的频率、占空比、放大系数、衰减系数等参数，也支持输入任意信号的表达式。同时具有频谱分析的功能，设定采样频率后即可对信号进行频谱分析。

10.1 关联规则基本概念10.2 关联规则算法原理10.3 分层搜索经典算法-Apriori算法10.4 并行挖掘算法10.5 增量更新挖掘算法10.6 多层关联规则挖掘10.7 多维关联规则挖掘10.8 约束性关联规则挖掘10.9 数量关联规则挖掘10.10 负关联规则挖掘算法10.11 加权关联规则挖掘算法10.12 应用实例分析10.13 小结

XH2.54系列插头Altium封装，包含3D模型，辛苦赞起来的