STM32F4驱动线阵CCD——TCD1304

Hyres 3.1(分辨率测试软件) 和ISO12233测试标板的使用和判读，有兴趣的童鞋可以看看。

基于kalman滤波的meanshift算法 代码可供参考 效果一般

我自己在实验课上做的步进电机的程序和仿真，实现电机的正转、反转和停止功能，转速可根据延时自己调节

请低调使用！请低调使用！请低调使用！请低调使用！请低调使用！请低调使用！解压后包括：1套是源码文件（每种组件一个文件夹），1个是一键编译安装工具，1个是汉化文件。拥有180多种VCL界面控件，功能丰富且易于上手 DevExpress VCL Subscription 是 Devexpress公司旗下用户界面产品套包，包含该公司所有VCL控件产品和 ASP.NET控件产品以及相关产品的完整源码。所包含的控件有：数据录入，图表，数据分析，导航，布局，网格，日程管理，样式，打印和工作流等，让您快速开发出完美、强大的VCL应用程序！DevExpress VCL Subscription

这是用于手写数字识别的lenet-5模型的MATLAB 代码，内有数据集可以直接运行

ftp简介，协议说明，使用FTP协议FTP简介文件传输协议（FTP）作为网络共享文件的传输协议，在网络应用软件中具有广泛的应用。FTP的目标是提高文件的共享性和可靠高效地传送数据。FTP协议中使用两个Socket, 将命令与数据分开传送的方法提高效率。FTP 使用 2 个端口，一个数据端口和一个命令端口（也叫做控制端口）。命令端口一般是21 （命令端口）和数据端口一般20。控制Socket用来传送命令，数据Socket是用于传送数据。客户端每一个FTP 命令发送之后，FTP服务器都会返回一个字符串，其中包括一个响应代码和一些说明信息。返回码用于判断命令是否被成功执行了 FTP模式主动模式：客户端随机打开一个大于 1024 的端口向服务器的命令端口（21），发起连接，同时开放N 1 端口监听，并向服务器发出“port N 1”命令，由服务器从它自己的数据端口 (20) 主动连接到客户端指定的数据端口 (N 1)。FTP 的客户端只是告诉服务器自己的端口号，让服务器来连接客户端指定的端口。对于客户端的防火墙来说，这是从外部到内部的连接，可能会被阻塞 注：1. 数据传输通道是在有数据传输的行为才会建立连接，并不是一开始连接到FTP服务器就立刻建立的数据通道2. port 21接受来自客户端的主动连接，port 20则是FTP服务器主动连接到客户端被动模式客户端通过PASV命令获得服务器端IP地址和数据端口，然后向服务器端发起连接请求，从而建立数据连接。服务器端只是被动地监听在指定端口上的请求1. 客户端与服务器建立命令通道2. 客户端发起PASV的连接要求3. FTP服务器启动数据端口，并通知客户端连接4. 客户端随机取用大于1024的端口进行连接 注:被动模式FTP数据通道是由客户端向服务器端发起连接的 FTP命令及响应命令:FTP命令按照ASCII格式在控制连接上传输(命令可读)，每个命令后跟回车换行符 （）USER username 向服务器传输用户名PASS password 向服务器传输密码CWD 跳转目录QUIT  从服务器上退出FTP登入 RETR filename  从远程主机获取文件STOR filename  向远程主机当前目录存储文件，如存在同名文件则覆盖MKD   在服务器上建立目录APPE   追加（包括创建）LIST   请求服务器返回远程主机当前目录下的所有文件列表NOOP   该命令不指定任何动作 ， 只是要求服务器返回OK响应 响应:命令发送后，服务器会发送相应的响应给客户端说明情况。响应是一个3位数字（xyz），后面跟一些文本信息供直接查看响应的第一位数字(x)：1：预备状态2：完成状态3：中间状态4：暂时拒绝状态5：永久拒绝状态响应第二位数字(y):0: 语法-这种响应指出了语法错误。给出的命令不存在、没有被实现、或多余1: 信息-对于请求信息的响应，比如对状态或帮助的请求2: 连接-关于控制连接和数据连接的响应3: 身份验证和帐户-对登陆过程和帐户处理的响应4: 目前还未使用5: 文件系统-请求传输时服务器文件系统的状态或其他文件系统动作状态

有了这个就不用去买参考书了！省下不少钱！

ds 证据理论 python 代码

MIPI Alliance Specification for D-PHY Version 1.00.00 – 14 May 2009配合“MIPI Alliance Specification for Camera Serial Interface 2 (CSI-2)“ 一起看。http://download.csdn.net/detail/micro_st/4242724Version1.00.0014-May-2009MIPI Alliance Specification for D-PHY2 The material contained herein is not a license, either expressly or impliedly, to any IPR owned or3 controlled by any of the authors or developers of this material or MIPl. The material contained herein is4 provided on an"as iS basis and to the maximum extent permitted by applicable law, this material is5 provided AS IS AND WITH ALL FAULTS, and the authors and developers of this material and MIP6 hereby disclaim all other warranties and conditions, either express, implied or statutory, including, but not7 limited to, any (ifany)inplied warranties, duties or conditions of merchantability, of fitness for a8 particular purpose, of accuracy or completeness of responses, of results, of workmanlike effort, of lack of9 viruses, and of lack of negligence10 All materials contained herein are protected by copyright laws, and may not be reproduced, republisheddistributed, transmitted, displayed, broadcast or otherwise exploited in any manner without the express12 prior written permission of MIPI Alliance. MIPl, MIPI Alliance and the dotted rainbow arch and all related3 trademarks, tradenames, and other intellectual property are the exclusive property of MIPI Alliance and14 cannot be used without its express prior written permission15 ALSO, THERE IS NO WARRANTY OF CONDITION OF TITLE, QUIET ENJOYMENT, QUIET16 POSSESSION. CORRESPONDENCE TO DESCRIPTION OR NON-INFRINGEMENT WITH17 REGARD TO THIS MATERIAL OR THE CONTENTS OF THIS DOCUMENT.IN NO EVENT WILLI8 ANY AUTHOR OR DEVELOPER OF THIS MATERIAL OR THE CONTENTS OF THIS DOCUMENT9 OR MIPI BE LIABLE TO ANY OTHER PARTY FOR THE COST OF PROCURING SUBSTITUTE20 GOODS OR SERVICES. LOST PROFITS. LOSS OF USE. LOSS OF DATA OR ANY INCIDENTAL.21 CONSEQUENTIAL, DIRECT, INDIRECT, OR SPECIAL DAMAGES WHETHER UNDER22 CONTRACT TORT WARRANTY OR OTHERWISE ARISING IN ANY WAY OUT OF THIS OR23 ANY OTHER AGREEMENT SPECIFICATION OR DOCUMENT RELATING TO THIS MATERIAL24 WHETHER OR NOT SUCH PARTY HAD ADVANCE NOTICE OF THE POSSIBILITY OF SUCH25 DAMAGES26 Without limiting the generality of this Disclaimer stated above, the user of the contents of this Document is27 further notified that MIPI: (a)does not evaluate, test or verify the accuracy, soundness or credibility of the28 contents of this Document;(b)does not monitor or enforce compliance with the contents of this Document29 and (c)does not certify, test, or in any manner investigate products or services or any claims of compliance30 with the contents of this Document. The use or implementation of the contents of this Document may31 involve or require the use of intellectual property rights ("IPR")including(but not limited to) patents32 patent applications, or copyrights owned by one or more parties, whether or not Members of MIPIMIPI33 does not make any search or investigation for IPR, nor does miPi require or request the disclosure of any34 IPR or claims of IPR as respects the contents of this document or otherwise35 Questions pertaining to this document, or the terms or conditions of its provision, should be addressed36 MIPI Alliance. Inc37 c/o IEEE-ISTO38 445 Hoes lane39 Piscataway, NJ0885440 Alin: Board SecretaryCopyright C 2007-2009 MIPl Alliance, Inc. All rights reservedMIPI Alliance Member ConfidentialVersion1.00.0014-May-2009MIPI Alliance Specification for D-PHY42 Contents43 Draft Version 1.00.00-14 May 2009441 Overview1451.2 Purpose.…..,.,.,,.,..472 Terminology…2.1 Definitions162.2 Abbreviations…172.3 Acronyms51 3 D-PHY Introduction523.1 Summary of Phy functionality533.2 Mandatory Functionality················2054 4 Architecture21554.1 Lane modules…564.2 Master and slave2254.3 High Frequency Clock Generation22584.4 Clock lane data lanes and the phy-Protocol interface.224.5 Selectable Lane Options·;····················234.6 Lane Module Types4.6.1 Unidirectional Data Lane…264.6.2 Bi-directional data lanes26634.6.3 Clock lane.274.7 Configurations….7654.7.1 Unidirectional Configurations............664.7.2Bi-Dal Half-Duplex Configurations674.7.3 Mixed Data Lane configurations32Copyright C 2007-2009 MIPl Alliance, Inc. All rights reservedMIPI Alliance Member Confidential111Ⅴ ersion1.00.0014-May-2009MIPI Alliance Specification for D-PHY695.1Transmission Data Structure,………………………∴335.1.1Data unitsa勹5.1.2 Bit order Serialization and De-Serialization33725.1.3 Encoding and decoding735.1.4 Data Buffering,33745.2 Lane States and Line levels755.3 Operating Modes: Control, High-Speed, and Escape5. 4 High-Speed Data Transmission··········;·5. 41 Burst payload data785.4.2 Start-of-Transmission795.4.3End-of-transmission805.4.4 HS Data Transmission burst.365.5 Bi-directional data Lane turnaround5.6 Escape Mode41835.6.1Remote triggers42845.6.2 Low-Power data Transmission43855.6.3 Ultra-Low Power State865.6.4 Escape Mode State Machine43875.7 High-Speed Clock Transmission885. 8 Clock lane Ultra-Low Power State50959 Global Operation Timing Parameters.……5.10 System Power States56915.11 Initialization56925.12 Calibration5.13 Global Operation Flow Diagram57945.14 Data Rate Dependent Parameters(informative)955. 14.1 Parameters Containing Only UI values965. 14.2 Parameters Containing Time and Ul values59Copyright C 2007-2009 MIPl Alliance, Inc. All rights reservedMIPI Alliance Member ConfidentialVersion1.00.0014-May-2009MIPI Alliance Specification for D-PHY5.14.3 Parameters Containing Only Time Values…………5.14.4 Parameters Containing Only Time Values That Are Not Data Rate Dependent6 Fault detection611006.1 Contention detection1016.2 Sequence Error Detection.……611026.2.1 SoT Error621036.2.2 SOT Sync Error1046.2.3 EoT Sync Error1056.2. 4 Escape Mode Entry Command error.1066.2.5 LP Transmission Sync error621076.2.6 False Control error1086.3 Protocol Watchdog Timers(informative)62l096.3.1 HS RX Timeout6.3.2HS TX Timeout………………·················+···:··:·················∴62l116.3.3Escape mode timeout62l126.3. 4 Escape Mode Silence Timeout6.3.5 Turnaround errors114 7 Interconnect and Lane Configuration.641157.1 Lane configuration1167.2 Boundary Conditions.....…647.3 Definitions………64l187.4S- parameter Specifications………….651197.5 Characterization Conditions207.6 nterconnect Specifications………1217.6.1 Differential characteristics1227. 6.2 Common-mode characteristics671237.6.3 Intra-Lane Cross-Coupling1247. 6. 4 Mode-Conversion limitsCopyright C 2007-2009 MIPl Alliance, Inc. All rights reservedMIPI Alliance Member ConfidentialVersion1.00.0014-May-2009MIPI Alliance Specification for D-PHY1257.6.5 Inter-Lane Cross-Coupling671267. 6.6 Inter-Lane static skew1277.7 Driver and receiver Characteristics1287.7.1 Differential Characteristics1297. 7.2 Common-Mode characteristics1307.7.3 Mode-Conversion Limits1317.7.4 Inter-Lane Matching132 8 Electrical Characterislics701338.1 Driver characteristics1348.1.1 High-Speed Transmitter1358.1.2 Low-Power Transmitter1368.2 Receiver Characteristic·…············…·······…8301378.2.1 High-Speed Receiver801388.2.2Low- Power receiver.................….….821398.3 Line contention detection1408.4 Input Characteristics8441 9 High-Speed Data-Clock Timing1429.1 High-Speed Clock Timing861439.2 Forward High-Speed Data Transmission Timing871449.2.1 Data-Clock Timing Specifications1459.3 Reverse High-Speed Data Transmission Timing89146 10 Regulatory Requirements91147 Annex A Logical PHY-Protocol Inter face Description(informative)92148A 1 Signal Description149A 2 High-Speed Transmit from the Master Side150A3 High-Speed receive at the slave Sidel00151A 4 High-Speed Transmit from the Slave side152A.5 High-Speed Receive at the Master SideIOICopyright C 2007-2009 MIPl Alliance, Inc. All rights reservedMIPI Alliance Member ConfidentialVersion1.00.0014-May-2009MIPI Alliance Specification for D-PHY153A6 Low-Power Data Transmission102154A7 Low-Power Data Reception.103155A 8 Turn-around156 Annex B Interconnect Design Guidelines (informative)105157B. 1 Practical distances105158B 2 RF Frequency Bands: Interference.105B3 Transmission Line design160B4 Reference Layer.106161B 5 Printed-Circuit board106162B6 Flex-foils106163B 7 Series resistance106164B 8 Connectors106165 Annex C 8b9b Line Coding for D-PHY(normative)107166C 1 Line Coding Features...·············108167C.1.1Enabled Features for the Protocol108l68C 1. 2 Enabled Features for the Phy108169C2 Coding scheme170C 2.1 8b9b Coding Properties.....108171C 2.2 Data Codes: Basic Code Set……….109C.2.3 Comma Codes: Unique Exception Codes110173C 2.4 Control Codes: Regular Exception Codes…10174C.2.5 Complete Coding Scheme………175C 3 Operation with the D-PhY…11117yload: Data and Control177C.3.2 Details for Hs transmission………112178C.3.3 Details for LP Transmissionl12179C 4 Error Signal180C5 Extended PplCopyright C 2007-2009 MIPl Alliance, Inc. All rights reservedMIPI Alliance Member ConfidentialⅤ ersion1.00.0014-May-2009MIPI Alliance Specification for D-PHYl81C.6 Complete Code Set.….….l15182Copyright C 2007-2009 MIPl Alliance, Inc. All rights reservedMIPI Alliance Member Confidentialv111Version1.00.0014-May-2009MIPI Alliance Specification for D-PHYl83Figures184 Figure 1 Universal Lane Module functions21185 Figure2 Two Data Lane PHY Configuration.…………23186 Figure 3 Option Selection Flow Graph4187 Figure 4 Universal Lane Module Architecture25188 Figure 5 Lane Symbol Macros and Symbols Legend189 Figure 6 All Possible Data Lane Types and a basic Unidirectional Clock lane190 Figure 7 Unidirectional Single Data Lane Configuration30191 Figure 8 Unidirectional Multiple Data Lane Configuration without LPDT∴.30192 Figure 9 Two Directions Using Two Independent Unidirectional PHYs without LPDT.........31193 Figure 10 Bidirectional Single Data Lane Configuration31194 Figure 1l Bi-directional Multiple Data Lane Configuration......32195 Figure 12 Mixed Type multiple data Lane Configuration32196 Figure 13 Line level34197 Figure 14 High-Speed Data Transmission in Bursts36198 Figure 15 TX and rX State Machines for High-Speed Data Transmission37Figure16 Turnaround Procedure.……39200 Figure 17 Turnaround State Machine40201 Figure 18 Trigger-Reset Command in Escape Mode202 Figure 19 Two Data Byte Low-Power Data Transmission Example203 Figure 20 Escape Mode State Machine204 Figure2 I Switching the Clock Lane between Clock Transmission and low- Power mode………….47205 Figure 22 High-Speed Clock Transmission State Machine49206 Figure 23 Clock Lane Ultra-Low Power State State Machine········+·+···+·4···207 Figure 24 Data Lane Module State Diagram57208 Figure 25 Clock Lane Module state diagram58209 Figure 26 Point-to-point InterconnectCopyright C 2007-2009 MIPl Alliance, Inc. All rights reservedMIPI Alliance Member Confidential

matlab代码，利用Farrow结构设计分数延时滤波器，滤波器阶数和个数可分别进行设置，利用最大最小准则近似