verilog实现二维卷积设计

本程序为四路抢答器verlog HDL语言工程实例。(This program is four Responder verlog HDL language engineering examples.)

this describes building spi block on verilog hdl and programming them on an fpga device

一些对初学者比较实用的源码，ASK，PSK，FSK调制解调(Some of the more practical source code for beginners)

数字锁相环 dpll的 编译通过,使用verilog HDL语言对锁相环进行基于FPGA的全数字系统设计,以及对其性能进行分析和计算机仿真的具体方法(Digital phase-locked loop dpll compiler through the use of verilog HDL language on the phase-locked loop FPGA-based digital system design, as well as its performance analysis and computer simulation of specific methods)

v6 1x 3.125G rapidio协议工程代码(xilinx v6 rapidio data transmission protocol Practical project application engineering code)

友晶 altera DE2开发板中文用户手册，对DE2开发板的完整介绍。(DE2 development board Chinese user manual, a complete description of the DE2 board.)

基本功能的cpu，自定义内存内容~了解CPU运作原理~(design of cpu,VHDL environment~)

目前最新的OVL库，里面是标准的ASSERTION模块，支持VHDL刚Verilog，最近在做AXI协议验证的时候用到，分享下(The latest OVL(open verification library),including all standard module of assertions(VHDL and Verilog). It can be used into AXI Protocl Verification. Just share with you guys.)

用FPGA平台，5幅图片128*128的，存入rom中,按键控制停止和开始动画；

周立功Fusion StartKit，fpga开发板的实验例程，Flash Memory初始化RAM实验(ZLG Fusion StartKit, fpga development board test routines Flash Memory Initialize RAM experiments)