verilog实现二维卷积设计

EasyWifiRadar.zip r ok

计算机组成与设计课程设计 用verilog与FPGA设计多周期CPU 通过modelsim仿真与ISE综合

资源描述关于集成电路相关的所有面试问题。

Quartus2环境下基于VHDL状态机的交通灯程序(VHDL state machine traffic lights based on Quartus2 environment)

A controller for DDR2 on FPGA with vhdl, content testbench, model and textfile-generation/data-detection using python.

自己用verilog编写的crc16-ccitt码的产生，是并行的。(Crc16-ccitt code written in verilog generate parallel.)

About 1588 PTP protocol xillinx FPGA running code and Software application, and to introduce documents, want to help everyone

这是一个EOS项目中的GFP成帧结构，能够容错，可以配置字节域(This is an EOS project GFP Framing structure, be able to fault-tolerant, can be configured byte domain)

把指定的噪声叠加到信号上去.有标准噪声库NOISEX-92，其中带有白噪声、办公室噪声、工厂噪声、汽车噪声、坦克噪声等等，在信号处理中往往需要把库中的噪声叠加到信号中去，而噪声的采样频率与纯信号的采样频率往往不一致，需要采样频率的校准。 (The specified noise superimposed to the signal up. Standard noise library NOISEX-92, with white noise, office noise, factory noise, car noise, tank noise in the signal processing often requires noise to be superimposed in the library The signal to noise of the sampling frequency and pure signal sampling frequency is often inconsistent sampling frequency of calibration.)

ARTIX7200T FPGA 与PC 之间进行的以太网数据通信, 通信协议采用 Ethernet UDP 通信协议。FPGA 通过 GMII 总线或 MII总线和以太网PHY 芯片通信, 再把数据通过网线发给 PC，或者把从 PC 接收的以太网数据传给 FPGA。