I2C 异步子设备

实现数字变下频的matlab程序，CIC,HB,FIR滤波器代码都在其中(Realize digital variable frequency under matlab, CIC, HB, FIR filter code in it )

FPGA中常用的上升沿检测和下降沿检测代码以及检测是否有边沿，使用的verilog hdl语言，有几个写法，附带仿真时序，可以下载学习一下

这是基于verilog hdl的数字时钟源代码，能够实现时分秒的计时，可以手动进行调时与调分。(This is based on the digital clock verilog hdl source code, can be achieved when every minute of the time, you can adjust the time manually adjusting points.)

说明：  bnn-fpga是FPGA上CIFAR-10的二进制神经网络（BNN）加速器的开源实现。 加速器针对低功耗嵌入式现场可编程SoC，并在Zedboard上进行了测试。 在编写CIFAR-10测试集中的10000张图像时，错误率是11.19％。(bnn-fpga is an open-source implementation of a binarized neural network (BNN) accelerator for CIFAR-10 on FPGA. The architecture and training of the BNN is proposed by Courbarieaux et al. and open-source Python code is available. Our accelerator targets low-power embedded field-programmable SoCs and was tested on a Zedboard. At time of writing the error rate on the 10000 images in the CIFAR-10 test set is 11.19%.)

说明：  SPI协议的芯片验证VIP,用UVM搭建平台验证代码(Chip verification VIP of SPI protocol, build platform verification code with UVM)

有关gal器件的编程入门，以及常见逻辑门、计数器VHDL程序(For gal device programming entry, as well as common logic gates, counters VHDL program)

fpga模拟两路视频，简单拼接后，经过GPIF II接口传出给cy2014，测试usb的吞吐量(fpga generate two lane video, and transmit them through GPIF II interface. test cy2014)

vc707 board ucf xdc files

使用verilog hdl语言编程正弦波信号，能仿真出结果(Can use verilog HDL language programming sine wave signal, the simulation results )

Verilog 最大公约数设计RTL级代码和芯片设计图(Verilog GCD Design and synthesis layout )