verilog例子资源，对于初学者很有帮助。

FPGA实现串口发送 Verilog 语言(Serial reception FPGA Verilog language.)

USB2.0的VHDL描述，很经典了，欢迎大家下载-USB2.0 the VHDL description, very classic, and welcomes everyone to download

VHDL实现简单打地鼠游戏机，北邮数电实验(VHDL simple playing hamster games, BUPT number of electric experiment)

UART communication on SPARTAN 6 it contains tx and rx

一个开源mips处理器verilog 源码(wishbone interface wishbone interface)

Matlab code to simulation the wireless channel type.This is the most common case called Rayleigh channel.And in the frequency selective channel.

1、用状态机设计A/D转换器ADC0809的采样控制电路，并在数码管上显示转换结果； 2、设置有复位和启动/保持开关，要求 ⑴ 复位开关用来使A/D转换器复位，并做好A/D转换准备； ⑵ 启动/保持开关用来控制A/D转换器开始连续转换或停止转换保持结果，即按一下启动/保持开关，启动A/D转换器开始转换，再按一下启/停开关，停止转换并保持结果。 3、采用Verilog HDL语言设计符合上述功能要求的控制电路。(1, with the state machine design A/D converter ADC0809 sampling control circuit and display the results on the digital conversion 2 is provided with a reset and start/hold switch, reset switch is used to make the request ⑴ A/D converter reset and do A/D conversion ready ⑵ start/hold switch is used to control the A/D converter starts converting or stop the conversion to maintain a continuous result that by clicking Start/hold switch, start the A/D converter to start the conversion, and then Click the start/stop switch stops the conversion and keep the results. 3, using Verilog HDL language designed to meet the functional requirements of the above-mentioned control circuit.)

说明：  基于FPGA 黑金ALINX 515的 ADDA采样模块源码（需调试）(ADDA Sampling Module Source Code Based on FPGA Heijin ALINX 515)

基于BOOTH的32位快速乘法器的设计源码-BOOTH-based 32-bit fast multiplier design source

移位除乘法器带testbench好用的工程(Useful addition to the shift multiplier works with testbench)