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18_vga_test
基于Xilinx Spartan6系列的fpga的VGA实现(Based on Xilinx Spartan6 series fpga VGA implementation)
- 2019-04-01 13:47:46下载
- 积分:1
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UC1676C
51单片机测试程序,IC:UC1676,4线串口(51 MCU test program, IC:UC1676 4-LINE, SPI INTERFACE)
- 2020-10-17 11:17:28下载
- 积分:1
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uart
9针的rs232与fpga之间的串口通信源程序(Rs232 9 pin serial communication with the source between fpga)
- 2011-08-22 17:57:52下载
- 积分:1
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gmsk
产生高斯最小相移键控信号的阐述仿真,包括调制解调、信道模型等。(Simulation program to realize GMSK transmission system)
- 2020-11-14 19:49:42下载
- 积分:1
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FIFO
This is a simple example of FIFO(first in and first out) module written in verilog code(This is a simple example of FIFO (first in and first out) module written in verilog code)
- 2013-10-04 00:41:42下载
- 积分:1
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smartWasher
QUARTER编程环境实现的智能洗衣机系统,通过DE0板子进行模拟,组要完成洗衣机5个步骤的顺序过程以及系统相应动作(QUARTER programming environment of intelligent washing system, through simulation DE0 board, groups 5 to complete the washing process and the system the sequence of steps corresponding action)
- 2020-11-06 13:19:49下载
- 积分:1
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counter-with-T_FF
This is counter with T_FF.
- 2016-03-26 16:36:05下载
- 积分:1
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MAX48_cn
MAX481、MAX483、MAX485、MAX487-MAX491以及
MAX1487是用于RS-485与RS-422通信的低功耗收发器,
每个器件中都具有一个驱动器和一个接收器(The MAX481, MAX483, MAX485 The MAX487-MAX491, and MAX1487 low-power transceivers for RS-485 and RS-422 communication, each device has a drive and a receiver)
- 2012-07-10 21:28:46下载
- 积分:1
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FPGA实现1Gb以太网
简单的以太网例程,verilog语言,vivado环境
- 2022-01-28 12:02:23下载
- 积分:1
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esvl
MATLAB Filter Design HDL Coder
Simunlink HDL Coder
Xilinx ISE Webpack
- 2011-06-15 19:56:11下载
- 积分:1