nrf2401 FPGA接口驱动

2011年全国大学生电子设计竞赛E题“简易数字信号传输性能分析仪”fpga的控制代码，verilog编写；包括了M序列及同步时钟的提取等所有程序。(2011 National Undergraduate Electronic Design Contest E title "Simple digital signal transmission performance analyzer" fpga control code, verilog prepared including the M-sequence and synchronous clock extraction and all other programs.)

光纤发送接收模块，verilog编写，主要用于光纤的发送和接收，波长1310nm(Fiber optic transmitter receiver module, verilog written primarily for transmitting and receiving the optical fiber, wavelength 1310nm)

基于FPGA控制的DDS波形发生器，可在Cyclone IV系列板子上使用，已经过仿真验证(Based FPGA control DDS waveform generator in Cyclone IV series board on use, has been simulation)

Construction and Experimental Evaluations of User-Centered Power

基于FPGA的图像算法实现，包含了matlab的算法验证，利用xilinx的开发环境在FPGA上实现了算法，最终通过了验证。

The SPFD5408A, a 262144-color System-on-Chip (SoC) driver LSI designed for small and medium sizes of TFT LCD display, is capable of supporting up to 240xRGBx320 in resolution which can be achieved by the designated RAM for graphic data. The 720-channel source driver has true 6-bit resolution, which (The SPFD5408A, a 262144-color System-on-Chip (SoC) driver LSI designed for small and medium sizes of TFT LCD display, is capable of supporting up to 240xRGBx320 in resolution which can be achieved by the designated RAM for graphic data. The )

基于有限状态机的健壮性测试研究。 关键词：健壮性测试；增强有限状态机；全球平台；安全通道协议(The Research of Robustness Testing Based on FSM)

quartus2的中文文档，不是很全，仅供大家学习(quartus2 the Chinese document, not very wide, only for them to learn)

HART 官方资料-HART协议采用基于Bell202标准的FSK频移键控信号，在低频的4-20mA模拟信号上叠加幅度为0.5mA的音频数字信号进行双向数字通讯，数据传输率为1.2kbps。(Official information-HART HART protocol based Bell202 standard frequency shift keying FSK signal at low frequencies 4-20mA analog signal amplitude is 0.5mA superimposed on the two-way audio digital signal digital communication, data transfer rate of 1.2kbps.)

采用xilinx三太以太网ip核，tri-mode MAC完成千兆以太网数据传输(Too Ethernet using xilinx ip three nuclear, tri-mode MAC Gigabit Ethernet data transmission is completed)