一位LED显示的VHDL程序，挺简单的，买的开发板里面带的

说明：  Xilinx原语的使用介绍，特别全面，希望对大家有所帮助，(Introduction to the use of Xilinx primitives, particularly comprehensive,I hope it will be helpful to you all.)

alu 模块，算术逻辑单元，实现简单的控制模块，有最基本的几条指令-alu instruction

该部分的主要功能是完成基于FPGA的polar码SC译码。(The main function of this part is to complete the FPGA-based polar code SC decoding.)

a、设计可显示横彩条和纵彩条的VGA彩条信号； b、设计可显示英语字母的VGA彩条信号； c、设计可显示移动彩色斑点的VGA彩条信号； d、设计可实现手动切换a、b、c三个功能.(The design can display VGA color color and color of the longitudinal cross signal. The design can display the VGA color signal of the English alphabet. The design can display the VGA color signal of mobile color spots.)

用VERILOG编写的数字电子钟，用数码管进行显示时间-VERILOG prepared with digital electronic clock with a nixie tube display time

vhdl学习方法,含有大量的vhdl源代码,对vhdl的语法的介绍-VHDL source习laugh Yang, Yi bleed at the nose cavity submerged stresses measured tungsten Daitou VHDL, VHDL-Qin Pang Yang cavity cavity Geng Zhuang

用于实现FPGA硬件开发使用的加法器，需要注意的是用Verilog语言实现的(The adder used to realize FPGA hardware development needs to be realized in Verilog language)

描述了使用FPGA接口PDIUSBD12开发USB接口的流程.-Describes the use of FPGA Interface USB interface PDIUSBD12 development flow.

Learning Verilog Chinese Version Part 8

异步fifo实现，通过双口ram实现异步fifo(Asynchronous FIFO implementation, through dual port RAM to achieve asynchronous FIFO)