循环冗余校验码(试验报告)

AUDIO音频模块AN831的录音及播放FPGA代码，测试通过(AUDIO audio module AN831 recording and playback of FPGA code, the test passed)

说明：  acousting fingerprint enhancement

IEEE 802.3 Cyclic Redundancy Check参考设计，xilinx提供-IEEE 802.3 Cyclic Redundancy Check reference design for Xilinx

该项目是用VHDL编写的，并在Nexys2板套件的4个七段显示器中显示一个测微计的秒、分和小时。时间可以在开关0中停止，在按钮0中复位。显示方式与显示方式不同最小：分段到hr:min通过切换开关1

一个可以综合的Verilog 写的FIFO存储器 内附文档说明-a comprehensive Verilog can write FIFO memory attached document shows

ps2接口的工程实现，顶层为原理图，便于理解-ps2 interface engineering implementation, the top-level schematic diagram for easy understanding of

基于FPGA的自治型SPWM波形发生器的设计！正弦脉宽调制（SPWM）技术在以电压源逆变电路为核心的电力电子装置中有着广泛的应用，如何产生SPWM脉冲序列及其实现手段是PWM技术的关键。大家共同探讨哈！-FPGA based SPWM autonomy-based waveform generator design! Sinusoidal pulse width modulation (SPWM) technology in the voltage source inverter circuit as the core of the power electronic devices have a wide range of applications, how to generate SPWM pulse sequence and its implementation means PWM technology is the key. Kazakhstan investigate everyone!

Verilog HDL数字系统设计项目，频率可调的任意波形发生器，可以输出正弦波、方波、三角波和反三角四种波形(Verilog HDL digital system design projects, adjustable frequency arbitrary waveform generator can output sine wave, square wave, triangle wave and the anti-triangular four waveform)

参数可配置的sequential 乘法器和booth 乘法器(verilog source code with configurable parameters for sequential multiplier and booth multiplier )

altera推出的基于它们fpga和cpld的构建嵌入式系统的新技术sopc的介绍。其集成在quartus II中-ALTERA due to launch them and they simply cpld Construction of the new Embedded System Technology sopc briefing. Its integrated into the Quartus II