加法器（使用verilog编写的）,虽然简单，但是这也是学习verilog最基础的东西！希望大家一起学习！...

adding custom ip EDK

A program for a simple encoder using ModelSim6

说明：  基于EasyFPGA030的直流电机控制电路设计和四位数字密码锁。(DC Motor Control Based on EasyFPGA030 circuit design and four-digit combination lock.)

uart16550 ip core 通用异步收发器vhdl源代码-uart16550 ip core UART VHDL source code

一种基于FPGA 实现DDDR SDRAM的控制器 (DDDR SDRAM controller based on FPGA)

VHDL语言编程简单实例若干，适合于初学者(VHDL language programming simple example, suitable for beginners)

16位元浮点数CPU,可作运算,以VHDL编写-16-bit floating point CPU, can be used for computing in order to prepare VHDL

用verilog编程的TCON模块（时序控制器）的程序(Verilog programming module with TCON (timing controller) program)

design and implement a digital system on the Altera NIOS board which will read an analogue input using MicroChip’s SPI MCP3202 12-Bit A/D converter. The 8 most significant bits of the converted data will be displayed on two seven segments of the NIOS development board. The sampling frequency is 20kHZ. Use a potentiometer.(design and implement a digital system on the Altera NIOS board which will read an analogue input using MicroChip' s SPI MCP3202 12-Bit A/D converter. The 8 most significant bits of the converted data will be displayed on two seven segments of the NIOS development board . The sampling frequency is 20kHZ. Use a potentiometer.)

EP1C6_EP1C12核心板原理图，方便自己动手做板学习FPGA-EP1C6_EP1C12 core board schematics, do-it-yourself to do to facilitate learning FPGA board