xilinx pcie verilog code

这里是由控制程序从ROM模块读取图片信息，然后写入VGA接口。里面包括6副16*16的图片信息，在屏幕上出现小绿人的动画

de2 70 开发板的演示程序，verilog语言编写，视频输入输出(de2 70 development board demo program, verilog language written, video input and output)

实现了四bit计数器的功能，使用的是VHDL语言描述(Four-bit counter, using the VHDL language description)

主要是基于FPGA(EP2C8Q208I8)下的SRAM驱动，SRAM型号为IS61LV25616，程序语言为Verilog,开发环境为quartusII 7.0,为一工程，可直接下载到FPGA中，含电路图(Mainly based on FPGA (EP2C8Q208I8) driving under the SRAM, SRAM model IS61LV25616, programming language for Verilog, a development environment for quartusII 7.0, for a project, can be downloaded directly to the FPGA, including circuit diagrams)

用三个按键控制pwm输出 key0控制是选着显示/改变频率或占空比 key1控制增加 key2控制减少 数码管显示频率或占空比 频率单位默认Hz（500-20KHz） 占空比范围（0.1-0.9）(Control PWM output with three keys Key0 controls display/change frequency or duty cycle optionally Key1 controls the increase Key2 controls are reduced Digital tube display frequency or duty ratio Frequency unit default Hz (500-20khz) Duty cycle range (0.1-0.9))

this project is about FIR FIlter By VHdl codes in the ISE.

Control with DAC conversion

Vending Machine simulation using Moore sequence

(Springer Series in Advanced Microelectronics 51) Ayan Palchaudhuri, Rajat Subhra Chakraborty (auth.)-High Performance Integer Arithmetic Circuit Design on FPGA_ Architecture, Implementation and Desig

说明：  一个完整的雷达系统仿真MATLAB程序，非常具有参考价值(A complete radar system simulation MATLAB programs have great reference value)