基于VGA显示的10路逻辑分析仪

基于FIPS 180-4标准的SHA-1算法的verilog HDL实现，分模块分别实现(FIPS 180-4 standard SHA-1 algorithm-based verilog HDL sub-modules, respectively, to achieve)

说明：  基于无源蜂鸣器和矩阵按键的电子琴系统设计(design of Electronic Piano System Based on Passive Buzzer and Matrix Key)

rgmii接口通讯方式，用于FPGA以太网口开发(Rgmii interface communication mode)

说明：  vivado入门使用介绍，初学者入门学习(vivado Instructional pdf)

可调电阻AD5270的Verilog测试读写功能代码(a test code for AD5270 to write and read)

Use this multimeter to make precise electronic measurements and tests. Easy-to-read LCD readout, positive set selector switch and 32" leads. AC voltage

简单流水线CPU，使用 verilog实现，实现一条指令的整个流程(Implementation of Simple Pipeline CPU Verilog)

实现了四bit计数器的功能，使用的是VHDL语言描述(Four-bit counter, using the VHDL language description)

产生长度为100的随机二进制序列 发送载波频率为10倍比特率，画出过采样率为100倍符号率的BPSK调制波形（前10个比特） ，及其功率谱 相干解调时假设收发频率相位相同，画出x(t) 的波形，假设低通滤波器的冲激响应为连续10个1（其余为0），或连续12个1 （其余为0） ，分别画出两种滤波器下的y(t)，及判决输出（前10个比特） 接收载波频率为10.05倍比特率，初相位相同，画出x(t) 的波形，假设低通滤波器的冲激响应为连续10个1，画出两种滤波器下的y(t)，及判决输出（前20个比特） 采用DPSK及延时差分相干解调，载波频率为10倍比特率，画出a, b, c, d点的波形（前10个比特） DPSK及延时差分相干解调，载波频率为10.25倍比特率时，画出a, b, c, d点的波形（前10个比特） DPSK及延时差分相干解调，载波频率为10.5倍比特率时，画出a, b, c, d点的波形（前10个比特） (Produce random binary sequence of length 100 The transmission carrier frequency is 10 times the bit rate, draw a sampling rate of 100 times the symbol rate of the BPSK modulation waveform (first 10 bits), its power spectrum Coherent demodulation of assuming the same as the phase of the transmitting and receiving frequencies, and draw the waveform x (t), assuming that the impulse response of the low pass filter 10 consecutive 1 (the remainder is 0), or 12 consecutive 1 (the remainder is 0), y (t) is drawn under the two filters respectively, and the decision output (10 bits) The received carrier frequency is 10.05 times the bit rate, the same initial phase, draw the waveform x (t), assuming that the impulse response of the low pass filter of 10 consecutive 1, shown under two filter y (t), and decision output (20 bits) DPSK and delay differential coherent demodulation, the carrier frequency is 10 times the bit rate, draw a, b, c, d point of the waveform (first 10 bits) DPSK and delay)

矩阵求逆模块硬件实现,用verilog语言，基于ISE开发环境(implement of inverse matrix)