基于VGA显示的10路逻辑分析仪

说明：  实现简单的硬件加法器、除法器，实现源码文中注释(Realize simple hardware adder and divider, realize source code)

利用QuartusⅡ6.0对所设计的出租车计费器的VHDL代码进行仿真，并在FPGA数字实验系统上实现了该控制。(The Quartus II 6 is used to simulate the VHDL code of the designed taxi billing device, and the control is realized on the FPGA digital experiment system.)

AES加密算法verilog源码 This project is the hardware implementation of the  Advanced Encryption Standard with a key size of 128 bits. The implementation adheres to the FIPS-197 document which explains the same.The core can do both encryption as well as decryption.The documents aes_arch.doc and aes_tb_readme.txt give further details of the rtl implementation and test bench respectively. This code was written originally with 128 bit ports for both input and key but later converted to 64 bits each to save on i/o pins. It can be reverted back easily if one just changes the port widths and dispenses with the load signal in the top module and making approriate changes in process where load is used.Synthesis results have been included for Xilinx Spartan-3 device.The directory structure of the project is as under- AES128

此代码是 verilog 代码和斯巴达 6 模型规范代码。欢迎大家下载、试用。谢谢大家的支持。

实现FPGA对AD芯片AD7060的控制，程序代码的注释很多，易学易懂，适合初学者学习使用(it is good ...)

用verilog实现sd卡读写，亲测可用(Implementation of SD card read and write with Verilog)

fpga下使用的ip核代码 使用 axi full 实现dma功能 占用资源极少. 使用 axi full 实现dma功能 占用资源极少. 使用 axi full 实现dma功能 占用资源极少. 使用 axi full 实现dma功能 占用资源极少. 使用 axi full 实现dma功能 占用资源极少. 使用 axi full 实现dma功能 占用资源极少.

verilog 硬件编程实现bpsk调制(verilog hardware, programming bpsk Modulation)

vhdl golden reference guide

说明：  Ovo sto saljem je tutorijal 7 sa vhdlom