DPSK的FPGA调制

说明：  假设每个从设备中有可访问APB寄存器16个，位宽均为32比特，16个寄存器的访问地址计算方式为 基址 +　寄存器编号左移２位（byte 偏移）(Assuming that there are 16 accessible APB registers in each slave device, the bit width is 32 bits, and the access address of 16 registers is calculated by base address + register number left shift 2 bits (byte offset).)

4位密码锁，可设置密码，三次密码错误后，锁死，密码错误报警，密码错误红灯亮，密码正确绿灯亮，基于FPGA实现，Cyclone II  EP2C35F672C6 仅供参考

FPGA实现的卷积编码，1/2编码效率，可在此基础上改为其他码率，如2/3 3/4等

用verilog实现endat2_1驱动,并用signalTap捕捉信号。(Using verilog achieve endat2_1 drive and use signalTap capture signal.)

用verilog实现ldpc最小和译码算法(This code is for the decode of MS-algorithm based on LDPC.)

说明：  用VERILOG实现的，hdb3编码器和解码器，经过前仿真和后仿真成功(Achieved with the VERILOG, hdb3 encoder and decoder, after a successful pre-simulation and post simulation)

基于FPGA的电子密码锁设计与实现，语言是VHDL语言，有注释(FPGA-based design and implementation of electronic locks, language is VHDL language, annotated)

这些代码为 对于基本的FPGA使用模块beep进行了例化 在工程 系统级建模时只需要直接调用就好了(The code for the basic FPGA using the module beep instantiated only need to be called directly in the engineering system-level modeling like)

计算机组成与设计课程设计 用verilog与FPGA设计多周期CPU 通过modelsim仿真与ISE综合

以太网PHY层中的组成部分 8B10B编码器(Part of the Ethernet PHY layer in 8B10B encoder )