乘数 2 位数 4 位

维特比译码，卷积编码，verilog编写，2,1,2编码(Victor than decoding, convolution code, verilog write, 2,1,2 coding )

适用于NIOS II的1024点FFT C算法( 1024-point FFT C algorithm for NIOS II)

evga-indtube.h - Keytable for evga_indtube Remote Controller.

说明：  “基于 ROM 的 LCD图片显示实验 ”中利用 FPGA 片上存储资源存储图片，并通过 LCD接口将图片显示到 LCD屏幕上。但是由于 FPGA 片上存储资源有限，只能存储分辨率较小的图片(In the experiment of LCD image display based on ROM, FPGA on-chip storage resources are used to store pictures, and the pictures are displayed on LCD screen through LCD interface. However, due to the limited on-chip memory resources of FPGA, it can only store images with smaller resolution)

下面的文件，包括各种RTL代码一样，全加器，defparam例如，还包括位运算符，逻辑运算符和多家运营商，半加器，复用器，多路复用器。这可能会帮助你理解的Verilog整个概念。

this program is a simulation for Aloha

说明：  RISC 5级流水线CPU，带HAZARD处理(RISC 5 pipeline CPU with HAZARD processing)

FPGA，用VHDL语言产生可调的PWM波(FPGA, VHDL language adjustable PWM wave)

一个vivado和matalab混合编程的信号发生器，注意要把vivado里面的核文件路径改一下(A signal generator with mixed programming of vivado and matalab, pay attention to changing the path of the core file in vivado)

这是个关于verilog入门的文档，有同志对verilog感兴趣，可以下载此文档，以供参考。(This is a verilog entry on the document, there are comrades of the verilog interested, you can download this document for reference.)