乘数 2 位数 4 位

vhdl project at sbu uni in iran uart

说明：  基于quartus2的jk触发器设计，内含源码和仿真图(Jk flip-flop design based on the quartus2, containing source code and simulation diagram)

用三个按键控制pwm输出 key0控制是选着显示/改变频率或占空比 key1控制增加 key2控制减少 数码管显示频率或占空比 频率单位默认Hz（500-20KHz） 占空比范围（0.1-0.9）(Control PWM output with three keys Key0 controls display/change frequency or duty cycle optionally Key1 controls the increase Key2 controls are reduced Digital tube display frequency or duty ratio Frequency unit default Hz (500-20khz) Duty cycle range (0.1-0.9))

XAPP585 serdes_1_to_7 and serdes_7_to_1 data

用Verilog语言编写的产生正弦波和方波的程序(Generate sine and square wave Verilog language program)

i2c代码 可以从eeprom中写入并读出一字节数据  并用led显示   已调试成功

本源码为Nios II的开发示例,主要演示基于Nios II的uCOS的移植。开发环境QuartusII。 本示例十分经典，对基于SOPC开发的FPGA初学者有很大帮助。(The source code for the Nios II development of examples, mainly based on the Nios II shows the uCOS transplant. Development environment QuartusII. This example is very classic, FPGA-based SOPC development of great help for beginners.)

通过FPGA实现整数阶混沌系统，通过定点数的方式，全并行。(The realization of integer order chaotic systems through FPGA)

改自特权同学verilog语言写sdram测试程序；支持256M内存(verilog sdram )

adder 18b trong chuong trinh verilog