随机计数的计数器Verilog代码

基于32位乘法器和32位加法器的1024位乘法器加法器数量=3乘法器数量=1分别从两块SRAM取数输入，输出写入第三块SRAM

在VHDL结构体中用于描述逻辑功能和电路结构的语句分为顺序语句和并行语句两部分，顺序语句的执行方式十分类似于普通软件语言的程序执行方式，都是按照语句的前后排列方式顺序执行的。(VHDL structure in the body used to describe the logic function and circuit structure of the order of statements and expressions are divided into two parts in parallel statement, modalities for the implementation of the order of statement is very similar to ordinary language software program implementation, are in accordance with the statements before and after the arrangement of the order implementation.)

It is vhdl code for defining a finite state machine

Lab view using FPGA traing on lcd pannel

说明：  FPGA实现Jpeg压缩，和视频采集程序(Zynq - Main - register access Mio)

这是网上找到的一篇关于SDRAM 驱动的程序，注解非常详细，并且很有条理。但因为很久的程序了，所以忘记了出处，印象中是特权同学的。

有限状态机工作原理、设计方法、步骤等精要说明(Finite state machine working principle, design method, such as Essentials of steps to explain)

如何编写测试文件，，test bench的编写方法和是列，，总结的非常好的东西(how to code test bench in verilog)

一个AD4003的测试/控制程序，2Ms/s，18bit的AD高速AD芯片(A AD4003 test / control program, 2Ms/s, 18bit AD high speed AD chip)

SPI_Master_verilog_code