OFDM_Verilog实现

This is a running 10 bit led on VHDL code including switch to shift from increasing or decreasing

说明：  利用EGO1数模混合口袋实验平台上的蓝牙模块与板卡进行无线通信。使用支持蓝牙 4.0 的手机与板卡上的蓝牙模块建立连接，并且通过手机 APP 发送命令，控制 FPGA 板卡上的硬件外设。(The Bluetooth module on the EGO1 digital-analog mixed pocket experimental platform is used to communicate with the board. The Bluetooth 4.0-enabled mobile phone is used to establish a connection with the Bluetooth module on the board, and commands are sent through the mobile phone APP to control the hardware peripherals on the FPGA board.)

encoding and decoding of audio signal

xilinx zc706开发板Verilog流水灯源代码，适合刚开始接触FPGA的程序员，新接触xilinx ZYNQ-7000 zc706套件开发板的菜鸟，资源包含设计程序，仿真程序、综合程序，很简单的代码，适合初学者

整合的OFDM调制解调方法，matlab文件，modelsim仿真(Integration OFDM modulation and demodulation method, matlab file, modelsim simulation)

Dynamic Power Management for the Iterative Decoding of Turbo Codes

very good code for edge detection based on vhdl programming.

该源代码下载之Altera官网，使用于Altera公司提供的3C120板子，但是里面的千兆以太网的程序还是可以借鉴的。它使用了Altera公司提供的Triple-Speed-Ethernet的IP核构建了Qsys系统，然后在nios2中编写程序。

说明：  一个1MHz的FIR低通滤波器。 ① 时钟信号频率16MHz; ② 输入信号位宽8bits，符号速率16MHz； ③ 要求在Matlab软件中进行FIR滤波器浮点和定点仿真，并确定FIR滤波器抽头系数； ④ 写出测试仿真程序。(A 1MHz FIR low pass filter. (1) The clock signal frequency is 16MHz; (2) The input signal has a bit width of 8 bits and a symbol rate of 16 MHz; (3) Floating-point and fixed-point simulation of FIR filter is required in Matlab software, and tap coefficients of FIR filter are determined. (4) Write the test simulation program.)

图像滤波中的中值滤波，有效滤除椒盐噪声，使用verilog语言编写(Image filtering in the median filter, effectively filter out salt and pepper noise, using verilog language)