设计和ASIC平台实现DDR SDRAM控制器

针对电力电子领域的需求，采用自然采样法设计了一个全数字三相SPWM信号产生系统IP软核．通过数字频率合成技术实现了对电源频率的辅确控制．使电源频率精度达到16位．其中。通过调节控制参数．分别实现了电源频率与载波频率的7级、8级控制．最后。搭建了基于FPGA的测试系统．验证了系统功能的正确性．(According to the requirement of power electronics, the natural sampling method for the design of a full digital three-phase SPWM signal generation system. The power frequency of IP core is the auxiliary control is implemented through digital frequency synthesis technology. The power frequency accuracy of 16. By adjusting the control parameters, 7 and 8 levels of power frequency and carrier frequency are realized respectively. Finally, the control of the power frequency and carrier frequency is realized. A test system based on FPGA is built, which verifies the correctness of the system function)

高级加密标准（英语：Advanced Encryption Standard，缩写：AES），在密码学 请点击左侧文件开始预览 ！预览只提供20%的代码片段，完整代码需下载后查看 加载中 侵权举报

应用背景创建一个新的Quartus II工程将用于在Altera DE2的电路实现—系列板。这个项目应该包含一个包含适当的输入和输出的顶级模块在Altera板端口。实例化你的处理器在顶层模块。使用开关sw15−0驱动该处理器使用开关SW17驱动运行输入DIN输入端口。同时，利用按键KEY0在时钟resetn和KEY1。将处理器总线导线ledr15−0和连接完成信号以LEDR关键技术该项目可用于8位处理器验证。你可以设计你自己的8位处理器，它通过验证代码。该代码用于verilog平台

介绍分频器的好资料。不光有奇数分频、偶数分频，还有小数分频。相信把这个资料理解透了后以后分频器的设计就不是问题了。(Introduction divider good information. Not only have an odd frequency, even frequency, there are fractional. I believe understanding this information through the post after the Divider is not a problem.)

基于xilinx spartan 3E开发板，通过旋转编码器实现流水灯的左右移动闪烁变换。(Based on the Xilinx Spartan 3E development board, the left and right flicker transformation of the flow lamp is realized by the rotary encoder.)

说明：  基于ESS303开发板的OV7670_VGA拍照功能实现(Implementation of OV7670_VGA camera function based on ESS303 development board)

设计了一个电子时钟，功能包括定点报时，设置闹钟，校时等(Designed an electronic clock, features include fixed-point timekeeping, setting alarms, school hours, etc.)

Laurent程序,用于CPM信号的调制,接收和分解,译码,以及判断(Laurent procedures for CPM modulation of the signal, and decomposition receiving, decoding, and to determine)

these are verilg prgms

verilog测试，fpga测试片外sramis61lv25616，256个k个字，16位，比较难调(it is fpga is 61lv25616 simple verilog program,complete sram read and write.it can read and write .)