4阶24倍抽取CIC滤波器设计

CH341A的I2C接口Labview all vision (CH341A I2C Labview)

这是基于Quartus2 开发环境和verilog hdl语言写的38译码器(This is based development environment and Quartus2 verilog hdl language used to write decoder 38)

ADI JESD204接口的ADC与Xilinx FPGA接口IP，包含Verilog和VHDL源代码，AXI总线接口，ADC串行控制接口(ADI IP for interfacing JESD204 ADC to Xilinx FPGA, include Verilog/VHDL source code, AXI interface and serial config interface )

对赛灵思7系列的三种型号的FPGA进行了综述(xilinx 7 productin overview)

2011年全国大学生电子设计竞赛E题“简易数字信号传输性能分析仪”fpga的控制代码，verilog编写；包括了M序列及同步时钟的提取等所有程序。(2011 National Undergraduate Electronic Design Contest E title "Simple digital signal transmission performance analyzer" fpga control code, verilog prepared including the M-sequence and synchronous clock extraction and all other programs.)

一个关于VERILOG与VHDL混合编程，混合验证的资料(A hybrid programming on VERILOG and VHDL, mixed verification data)

使用verilog语言实现锯齿波的产生，完美调试成功(The use of Verilog language to produce sawtooth waves)

台湾IC中心VHDL讲义，内容详细，适合IC前端设计参考(Taiwan s IC Center VHDL handouts, detailed reference design for front-end IC)

说明：  自适应滤波器算法LMS ，的FPGA实现，采用VERILOG实现。(LMS, an adaptive filter algorithm, is implemented on FPGA and VERILOG.)

AD采集模块,设计模块采集AD5270的输出数据(AD Collection module Design module to collect the output data of AD5270 )