VHDL language learning paradigm, the FSK

Sample behavioral waveforms for design file sin_rom.vThe following waveforms show the behavior of altsyncram megafunction for the chosen set of parameters in design sin_rom.v. For the purpose of this simulation, the contents of the memory at the start of the sample waveforms is assumed to be ( 3F0, 3F1, 3F2, 3F3, ...). The design sin_rom.v has one read port. The read port has 1024 words of 10 bits each. The output of the read port is unregistered. Fig. 1 : Wave showing read operation. The above waveform shows the behavior of the design under normal read conditions. The read happens at the rising edge of the enabled clock cycle. The output from the RAM is undefined until

实现时分秒的计数和校正实现时分秒的计数和校正(Realized and correction of minutes and seconds count)

说明：  Micron公司m73a系列nand flash仿真模型及测试文件(micron m73a series nand flash simulation model and testbench)

VHDL 2FSK调制解调器各部分的原理与代码(The principle and code of each part of the VHDL 2FSK modem)

利用单片机控制LED时钟显示，以及闹钟，程序较大，但比较简单易懂。(LED clock display)

说明：  stepper motor module on spartan 6 and 24MHz clock fequency

设计一个可容纳四组参赛的数字式抢答器，每组设一个按钮供抢答使用。抢答器具有第一信号鉴别和锁存功能，使除第一抢答者外的按钮不起作用；设置一个主持人“复位”按钮，主持人复位后，开始抢答，第一答对一次加1分，答错一次减1分

James Armstrong VHDL Design , source code

altera公司cycloneII全系列说明书，实用-altera" s cycloneII a full range of manual, practical

数字频率计 数字频率计-Digital frequency meter digital frequency meter