VHDL language learning paradigm, the FSK

Real time Clock DS1307 interacing with PIC using I2C.

初学学习verilog的经验，可以帮助新手以正确的思维方式，学习方法学习。(Verilog learning experience)

数字系统设计报告，多功能电子钟，显示年月日星期时分秒，及校时等功能(Digital system design report, multi-functional electronic bell, show date when the minutes and seconds a week, and school functions when)

请注意： 本例的源描述包含文件类型，在学习版上不能编译及模拟， 如果您需要对此描述进行编译及模拟，请与北京理工大学 ASIC研究所联系。 另外，此例与第75例是同一个电路的不同部分的描述，可以 一起参考这两个例子的描述。-Please note : The cases include the description of the source file type, version of the study can not be compiled and simulation, if you need to compile this description and simulation, Beijing Polytechnic University and the Institute of ASIC link. Additionally, the cases of 75 cases with the first of a circuit with the different parts of the description, reference together two examples of this description.

说明：  FPGA锁相环实验： 顶层文件加底层IP文件构成 top中例化ip核pll(Experiment of Phase-Locked Loop Based on FPGA)

VGA显示程序VHDL版本，适用于ALTERA的CPLD(VGA display program applies ALTERA CPLD)

VHDL Programmes -2 for dumping on FPGA

Xilinx的I2C总线控制器，verilog版本，文档号是XAPP333，可到Xilinx网上查找具体说明，有对应的VHDL版本的-Xilinx

this example exchanges the NRZ code to the MANCHESTER code with moore output

说明：  用FPGA于32进行SPI单向通信，FPGA向32放松发送数据(One-way SPI communication is carried out in 32 with FPGA, and data is sent to 32 with ease by FPGA.)