第八部分 EEPROM读写例程

Laurent程序,用于CPM信号的调制,接收和分解,译码,以及判断(Laurent procedures for CPM modulation of the signal, and decomposition receiving, decoding, and to determine)

verilog 典型电路设计包含各种常用电路的源码和详细的解释，适合新手使用(Verilog typical circuit design includes a variety of commonly used circuit source code and detailed explanations, suitable for beginners to use )

秒表 东北大学秦皇岛分校 电子设计自动化 实验(Stopwatch Northeastern University at Qinhuangdao electronic design automation experiment)

1K SRAM，安排字的32位，独立的读写端口，ASIC设计Verilog代码 采用偶校验对1的计数。 还带有测试平台

ahb single master single slave rtl design

实现二项混合式步进电机的驱动，和步进电机的细分程序。(The driving of binomial hybrid stepper motor and the subdivision program of stepper motor are realized.)

采用verilog实现的三级CIC抽取器，输入8位数据，输出26位数据，使用有限状态机用于实现下采样，包括积分器实现模块和梳状器实现模块

verilogPWM波的设计，属于数字电子技术实验入门的资料

基于FPGA的利用rom进行查询的方式生成一个频率为10KHZ的sin信号，编译成功，并实现功能仿真。(Query based on the the FPGA use of rom generate a frequency of 10 kHz sin signal, compiled successfully and to achieve functional simulation.)

NN CONTROLLER FOR UPQC