amba apb v2.0

一个1MHz的FIR低通滤波器。 ① 时钟信号频率16MHz; ② 输入信号位宽8bits，符号速率16MHz； ③ 要求在Matlab软件中进行FIR滤波器浮点和定点仿真，并确定FIR滤波器抽头系数； ④ 写出测试仿真程序。(A 1MHz FIR low pass filter. (1) The clock signal frequency is 16MHz; (2) The input signal has a bit width of 8 bits and a symbol rate of 16 MHz; (3) Floating-point and fixed-point simulation of FIR filter is required in Matlab software, and tap coefficients of FIR filter are determined. (4) Write the test simulation program.)

本程式為使用Verilog語言寫控制DRAM的控制模塊, 可以簡易的控制DRAM IC, 本程式已經過系統驗證.(program for the use of the Verilog language to write the control of DRAM control module, be easy to control DRAM IC, the program has been systematically verified.)

用Verilog写的基于MIPS架构的CPU，可以运行50多条指令，包括运算、分支、跳转、比较等指令，不过没有中断系统，大家可以考虑使用，我也是学校课程课设做的。。

实现SIGMA-DELTA Modulator的veriolog代码(sigma-delta moudulator for RFPLL )

这是维特比译码器 verilog 代码生成器进行测试和 FPGA 验证。

xilinx的时序约束实验，通过阅读本文档，你可以用全局时序约束来轻松提高已有的项目的系统时钟频率，同时你还可以用映射后静态时序报告以及布局布线后静态时序报告来分析你的设计性能(Xilinx timing constraints of the experiment, by reading this document, you can use the overall timing constraints to easily enhance existing projects the system clock frequency, at the same time you can also use static timing report after mapping, as well as after placement and routing static timing analysis report to you design performance)

STOPWATCH FPGA SEVEN SEGMENT DISPLAY

VHDL写时钟，分频模块什么，实现计时。定点报时，定点闹钟，显示年月日。(verilog HDL)

通过调用三速以太网IP核，上层实现ARP,TCP,UDP协议，以太网芯片是88E1111，绝对可用，支持千兆以太网，GMII接口。

说明：  2018全国大学生FPGA创新设计大赛南京总决赛封闭测试题目，以及自己编写的verilog和testbench，欢迎学习借鉴(The closed test topic of the 2018 National Undergraduate FPGA innovation design competition Nanjing finals, as well as Verilog and testbench compiled by ourselves, are welcome to learn)