LIFO堆栈实现(verilog)

MPSK调制与解调VHDL程序源代码与仿真(MPSK modulation and demodulation process and VHDL source code and simulation)

Float Point Add, Multiply, and Divide arithmetic. You can change and modify the add block and reuse it in FPGA or ASIC chip. The running clock is dependent of the technology you used in the ASIC. 

APB总线协议转I2C总线协议的接口IP，verilog代码实现，包含详细testbench(APB bus interface to I2C bus interface IP，verilog code )

通信中卷积交织/解交织FPGA源程序，采用verilogHDL代码实现，包含测试程序，经过验证。(Communication in the convolutional interleaving/de interleaving FPGA source program, using verilogHDL code to achieve, including test procedures, after verification.)

spartan6 里使用DDR3IP核，有教程以及源码(spartan6 with ddr3,source and tutorial)

verilog实现增量式PID算法，实测可用，带modelsim仿真(PID algorithm by verilog)

FPGA设计的四种常用思想与技巧，包括乒乓操作、串并转换、流水线操作、数据接口同步化(FPGA design of the four common ideas and techniques, including the operation of ping-pong, SERDES, pipelining, synchronization of data interface)

说明：  verilog实现的FFT变换，经硬件测试其功能与Altera的FFT IP核相近(verilog implementation FFT transform, through hardware, test its functionality with Altera' s FFT IP core similar to)

单片机和FPGA的通信程序，发送5个数，传输稳定，可以自行修改可一次传多个数(MCU and FPGA communication program, send five the number of stable transmission, you can modify the number may be more than one pass)

读取IGS数据中心提供的sinex文件 并恢复法方程(Read sinex file IGS data centers and to restore normal equation)