LIFO堆栈实现(verilog)

多相抽取滤波器。分四相，两倍抽取，采用16阶FIR滤波器实现(Polyphase decimation filters. Divided into four phases, extracted twice using 16-order FIR filter implementation)

system Verilog combinational logic

DDS信号源设计，有正弦波，方波，三角波，AM波，FM波，还有PSK,FSK,16QAM等多种信号产生。(DDS signal source design, there are sine, square wave, triangle wave, AM wave, FM wave, as well as PSK, FSK, 16QAM and other signal generation.)

QC LDPC的编码译码 代码与论文配套 是研究生毕设 可运行 代码风格优秀(QC LDPC Coding and Decoding Code and Paper Matching are Excellent Style of Running Code for Graduate Students)

本例程使用vivado2014.4工具，利用xilinx Basys3 实验板实现板载流水灯的两种模式控制。(This project uses verilog HDL to realize the the control of 16 leds loaded on Xilinx Basys3 board.)

vhdl数字电路设计经典教程，入门必备，非扫描版，非常清晰(vhdl digital circuit design classic handbook, entry-essential, non-scan version, very clear)

说明：  基于FPGA的串口发送和接收，使用的verlilog语言(Using Verilog serial port program, send and receive.)

使用Verilog HDL 语言在cyclone IV 上实现功能按键控制灯，主要目的是实现按键的消抖程序，加深理解Verilog HDL 语言的并行执行方式

HART 官方资料-HART协议采用基于Bell202标准的FSK频移键控信号，在低频的4-20mA模拟信号上叠加幅度为0.5mA的音频数字信号进行双向数字通讯，数据传输率为1.2kbps。(Official information-HART HART protocol based Bell202 standard frequency shift keying FSK signal at low frequencies 4-20mA analog signal amplitude is 0.5mA superimposed on the two-way audio digital signal digital communication, data transfer rate of 1.2kbps.)

FPGA按键加蜂鸣器实验： 加延时防抖+蜂鸣器(Experiments of keys and buzzers in FPGA)