主从 J-K 触发器

说明：  Use of Kalman and EKF on two-phase permanent magnet synchronous motor of the state estimate CDCDCDCDCCC

这是一个最最常用的用vhdl写的状态机，几乎哪儿都用得到(a very good state machine)

双时钟域FIFO(This is self-defined Dual-Clock FIFO, using logic lut resources. Dual-Clock FIFO, Depth: 256 Width: 32 USEDW: Y FULLL:Y EMPTY:Y)

用VHDL语言写了个FLAPPY_BIRD的程序，利用板子与屏幕可以运行游戏(VHDL language to write a program FLAPPY_BIRD by the board and the screen can run the game)

hdmi 视频编解码输入输出模块，verilog实现(hdmi encoder and decoder in verilog.)

一个用Verilog编写的编帧、解帧及码速匹配的程序，相当经典(Verilog prepared with a series of frames, frames and solutions yards speed matching procedures, rather classic!)

this describes building spi block on verilog hdl and programming them on an fpga device

说明：  用Verilog编写ad_9866的相应程序，在FPGA上实现相应功能(The corresponding program of ad_9866 is written with Verilog, and the corresponding functions are realized on the FPGA.)

说明：  使用verilog实现的双电梯控制器，1-9层，仿真通过(a bi-elevator controller written in VerilgHDL, which has floor1-9, simulation passed)

检测边缘（正或者负）并生成单一脉冲，脉冲持续 1 个时钟脉冲长度。 代码的测试台也包含在内。 如果你想同步不同信号过渡到异步信号，你会发现很有用，参考 https://www.doulos.com/knowhow/fpga/synchronisation/