fir 滤波，分块缩放

UART文件 包括发送器 接收器 fifo 测试文件(UART file includes a receiver transmitter fifo test files)

Verilog经典教程，很好的学习Verilog的书籍，对学习硬件编程很有帮助。(Verilog classic handbook, good learning Verilog books, to learn hardware programming helpful.)

说明：  用Verilog编写ad_9866的相应程序，在FPGA上实现相应功能(The corresponding program of ad_9866 is written with Verilog, and the corresponding functions are realized on the FPGA.)

VHDL Code For Full Adder By Data Flow Modelling

Syllabus for VSC-HVDC course

Based on SVPWM three-level inverter matlab simulation, It describes the application of load forecasting, EULER numerical analysis method.

it is a fir filter program VerilogHDL.(it is a filter program VerilogHDL fir.)

高速串行设计FPGA-GTX IP设置生成drp模块，可动态配置速率2.4Gbps，1.2Gbps，0.6Gbps，自适应链接(High-speed serial design FPGA-GTX IP setting generation drp module, dynamically configurable rate 2.4Gbps, 1.2Gbps, 0.6Gbps, adaptive link)

FPGA Implementation of QFT based Controller for a Buck type DC-DC Power Converter and Comparison with Fractional and Integral Order PID Controllers

用VHDL语言设计多功能的电子表。实现基本电子表的时间显示、闹钟、秒表等功能(VHDL language design with multi-functional electronic watch. The time table to achieve basic electronic display, alarm clock, stopwatch functions)