这是一个FPGA

I2C总线控制器 altera提供的VHDL的源程序代码-I2C Bus Controller ALTERA the VHDL source code

vhdl testbench的编写，textio的编写是一个难点，也是一个重点，而这是本人搜集的多篇关于textio的文章，同时附有简单注释!-vhdl testbench preparation, textio the preparation is a difficult, but also a focus, and this is my collection of articles on textio the article, at the same time with a simple note!

VHDL由简单存储器，计数器等搭建最终实现8位的cpu设计(VHDL realization 8 of cpu design)

Verilog 下脉冲发生器的源代码，可用于模拟三相交流电过零点，主要用于调试一些类似SVC（无功补偿）控制器的一些算法-Pulse generator under the Verilog source code, can be used to simulate three-phase alternating current zero-crossing point, mainly for debugging similar SVC (reactive power compensation) controller of a number of algorithms

简单流水线CPU，使用 verilog实现，实现一条指令的整个流程(Implementation of Simple Pipeline CPU Verilog)

VHDL_count 从 0 到 9 4 7 段 LED 显示 4 脉冲使 （đếm 慈 0 đến 9 hiển 施耐 4 带领 7 đoạn với 4 xung 启用）

Syplify经典英文教程。内含众多实验例程，Lab 1 Basic Synplify Run；Lab 2 Analyzing Critical Path and Assigning Timing；Lab 3 FSM (Finite State Machine) Compiler Constraints and Attributes(Syplify classic English tutorial. Contains numerous experiments routine, you can help learners to quickly grasp Syplify tips, is a rare foreign experiments tutorial.)

音乐计算器，可实现999以下加减法及与非运算功能，并能够播放两段音乐，可下载到FPGA板子上实现。(Music Calculator)

基于altera ep2c8双口RAM -Altera ep2c8-based dual-port RAM

说明：  vhdl cnn 您的帐号尚未开通，请上传编程资料开通或在线付费马上开通(vhdl cnnCategory: verilog All Download: FPGA_Based_CNN-master.zipSize:2.30 MB FavoriteFavorite Preview code View comments Description family:-app...)