基于FPGA的键盘程序代码，可用单片机控制

vhdl经典源代码――时钟设计，入门者必须掌握-vhdl classical source code-- Clock Design, beginners must master

反应速度测试小游戏，最小外设cpld游戏，带设计说明书(Reaction speed test games, the minimum peripheral cpld game, with design specifications)

Quartus环境下的7段扫描显示电路的源程序(Quartus environment of the seven scanning display circuit of the source)

线性伸展TDC的verilog，包含门级网表(TDC linear stretch of verilog, includes gate-level netlist)

实现矩阵相乘，即点积运算，为VERILOG语言。可以根据自己的需要改变维数，采用了流水线的结构(Achieve matrix multiplication, ie dot product operations, for VERILOG language. You can change the dimension according to their needs, using a pipeline structure)

可生成rom.初学者可以看看。很不错的。理解后生成rom很容易的。(LPM_ROM .It is good for VHDL new learner)

说明：  用于生成adams或recurdyn所需的路面不平度，用于悬架或其他的仿真(Adams or recurdyn used to generate the required road roughness for suspension or other simulation)

FPGA 点亮数码管的灯，本例程支持6位数码管，因为我的FPGA开发板是这样子的(The lamp of digital tube illuminated by FPGA)

数字钟，简单的数电应用，电子表源程序，常用也使用-watch

verilog编写随机数产生源程序，在硬件电路设计中应用广泛。本程序是在LFSR and a CASR 基础上实现的-random number generator to prepare Verilog source code, in the hardware circuit design applications. This procedure is in the LFSR and a CASR based on the