基于FPGA的键盘程序代码，可用单片机控制

用双端口ram实现异步fifo，采用格雷码，避免产生毛刺。-Using dual-port ram realize asynchronous fifo, the use of Gray code, avoiding the production of burr.

循环冗余校验码(试验报告)-Cyclic Redundancy Check (pilot reports)

二进制转十进制BCD码 Verilog语言 quartusII(Binary to decimal BCD code Verilog language quartusII)

实现A/D转换,给定输入，观察输出电压，VHDL程序。(Implement A/D conversion，Given input, observe the output voltage, VHDL program.)

先设计序列发生器产生序列：1011010001101010；再设计序列检测器，检测序列发生器产生序列，若检测到信号与预置待测信号相同，则输出“1”，否则输出“0”，并且将检测到的信号的显示出来。(First design sequence generator sequence: 1011010001101010 redesign sequence detector to detect sequence generator sequence, if the same signal is detected with the preset test signal output " 1" , otherwise " 0" , and the detection display signal out.)

基于 hdl语言的re232通信实验的设计，程序简单明了，一学就会(rs232 communication)

此设计采用Verilog HDL硬件语言设计,在掌宇开发板上实现. 将整个电路分为两个子模块，一个提供同步信号（H_SYNC和V_SYNC）及像素位置信息；另一个接收像素位置信息，并输出颜色信号。这样便于进行图形修改，同时也容易实现- This design uses Verilog the HDL hardware language design, realizes on the palm space development board Divides into two stature modules the entire electric circuit, provides the synchronized signal (H_SYNC and V_SYNC) and the picture element positional information; Another receive picture element positional information, and output color signal. Like this is advantageous for carries on the graph to revise, simultaneously is also easy to realize

说明：  Matlab源程序，包括插值计算、积分微分等。(Matlab source code, including the interpolation calculations, differential and so on.)

下采样与灰度

EDA常用计数函数VHDL程序设计，减法计数器：可预置数：-common counting function EDA VHDL programming, subtraction counter : Preset :