基于FPGA的键盘程序代码，可用单片机控制

说明：  浮点数加法器的源代码,实现浮点数的加法功能，浮点数遵循的是IEEE745标准(floating_piont addition)

基于FPGA的数字系统设计,包含原理、工程应用和案例。(FPGA-based digital system design, including theory, engineering applications and cases.)

canbus verilog实现，原代码文件-canbus verilog implementation, the original source document

第十章的代码。 本书通过100多个模块实例，详细地讲解了Verilog HDL程序设计语言，全书共分13章，内容涉及VerilogHDL语言基本概念、建模、同步设计、异步设计、功能验证等，实例包括各种加法器/计数器、乘法器/除法器、编码器/译码器、状态机、SPIMaster Controller、I2C Master controller、CAN ProtocolController、Memory模块、JPEG图像压缩模块、加密模块、ATA控制器、8位RISC-CPU等及各个实例模块相应的Testbench，所举实例具有很强的实用性和代表性，每个实例均给出了介绍、功能分析、程序代码和结果演示(Chapter X code. This book by more than 100 module instance, explain in detail the Verilog HDL programming language, the book is divided into 13 chapters, covering basic concepts VerilogHDL languages, modeling, synchronous design, asynchronous design, functional verification, etc. Examples include a variety of additions device/counters, multipliers/dividers, encoders/decoders, state machines, SPIMaster Controller, I2C Master controller, CAN ProtocolController, Memory modules, JPEG image compression module, encryption module, ATA controller, 8-bit RISC-CPU etc. and the various instances of the corresponding module Testbench, The examples are highly practical and representation, each instance of it all gives the introduction, functional analysis, program code and the results demonstrate)

    本资源详细的设计了一个FIFO的用法，将数据从ROM中读取送到FIFO缓存中然后RAM从FIFO缓存中读取数据存到内存中，改程序可以很好的学习三者之间的关系

实现有限域中乘法，输入二个普通二级制数，输出在本原多项式的乘法结果(Achieve limited multiplication field, enter the number of two-tier system of two ordinary output in primitive polynomial multiplication results)

用FPGA实现pwm调制波，通过单片机软核控制输入量来实现任意占空比方波的产生-wave

通过vga通讯控制显示器显示七彩条文，通过quartus编译的程序，可用-Communication and Control through the vga display colorful provisions quartus compiled through the procedures that can be used

顶级模块名称是 "_register32"。它包括许多包括 files(instance)、 _dff、 _dlatch、 和盖茨。 你可以看到整体的图表中，像 RTL 查看器后, 合成。 _register8 包含在顶部模块

VHDL 编写的RAM例子-RAM prepared VHDL example