基于FPGA的键盘程序代码，可用单片机控制

Verilog 最大公约数设计RTL级代码和芯片设计图(Verilog GCD Design and synthesis layout )

利用VHDL实现CPLD（EMP240T100C5）的PWM输出-Using VHDL realize CPLD (EMP240T100C5) of the PWM output

说明：  频率合成器实例模块设计。频率分辨率为32位DDS的VHDL程序(Frequency synthesizer module design example. 32-bit DDS frequency resolution of the VHDL program)

编写 VHDL 代码为 4 x 1 多路复用器，使用下面的方法 (1) if else 语句 (2) case 语句 (3) 与声明

EDA中很重要的小程序，保证按键可靠性，防止抖动误差信号产生，外部信号输入时必用此消抖函数-EDA very important small procedures to ensure that key reliability and prevent jitter error signal generated, the external input signal must use this function Consumers shiver

cpu微命令vhdl源代码-cpu-order VHDL source code

synopsys的systemc和RTl书籍清晰电子版，专业权威的EDA公司的培训资料(synopsys of systemc and RTl clear electronic version of books, professional authority of the EDA company' s training materials)

dual port ram control (dual port ram control dual port ram control dual port ram control)

VHDL 源码模块，可以实现最经典原PWM，可以用于电源，电机的控制()

DDS的VHDL程序，相当好，值得下载，共享才是王道(DDS, VHDL program is quite good, worth downloading, sharing is king)