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RS
说明: 通过verilog hdl语言实现RS编码器与译码器的设计(Verilog hdl language through the RS encoder and decoder design)
- 2013-07-18 16:09:22下载
- 积分:1
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Routine application of this experiment in the Actel Flash architecture ProASIC3/...
此实验例程适用于Actel Flash架构的ProASIC3/E系列FPGA,适合于FPGA及Verilog HDL的初学者,配套EasyFPGA030开发套件。-Routine application of this experiment in the Actel Flash architecture ProASIC3/E series FPGA, fit in the FPGA and Verilog HDL for beginners and supporting development kit EasyFPGA030.
- 2022-05-14 23:14:31下载
- 积分:1
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BLDC_Simplorer_Maxwell_Cosimulation
这个是永磁无刷直流电机的本体结构和控制电路的联合仿真,既可以设计电机的结构,又可以搭电机的控制系统。(This is the body structure of the permanent magnet brushless DC motor and control circuit co-simulation, both the structure of the motor can be designed, they can take control of the motor system.)
- 2021-03-26 11:39:13下载
- 积分:1
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FPGA代码,Designing_with_Quartus_II_Exercises_Ver11_v4_2.doc
FPGA代码,Designing_with_Quartus_II_Exercises_Ver11_v4_2.doc-FPGA code Designing_with_Quartus_II_Exercises_Ver1 1_v4_2.doc
- 2023-03-14 03:35:04下载
- 积分:1
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frequency divider
说明: FPGA对系统50M时钟进行分频。FPGA最基本功能基础(FPGA Verilog program, key detection, program jitter elimination, jitter elimination, delay detection keys)
- 2019-04-27 23:35:12下载
- 积分:1
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signal_capture
matlab 程序 伪随机码的捕获,我传的都是这方面的资料!(failed to translate)
- 2013-05-03 12:02:48下载
- 积分:1
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Shift_reg
一个简单移位寄存器代码,verilog HDL编写(a simple shift register example,write with verilog HDL)
- 2012-03-26 21:36:01下载
- 积分:1
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QPSK_1
QPSK调制,QPSK仿真误码率,QPSK理论误码率 , QPSK仿真误比特率 , QPSK理论误比特率 (QPSK modulation, the signal-to-noise ratio)
- 2020-12-06 19:29:22下载
- 积分:1
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VHDL电子钟的设计
(1)用HDL设计一个多功能数字钟,包含以下主要功能:精确计时,时间可以24小时制或12小时制显示;
(2)日历:显示年月日星期;
(3)能用QuartusII软件仿真;
- 2022-08-02 23:44:59下载
- 积分:1
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list_ch06_02_debounce
Eliminate the program of key bounce
- 2012-12-23 00:22:42下载
- 积分:1