cordic

verilog描述的实用消抖电路，采用三个D触发器和一个JK触发器。使用emacs编写源文件，iverilog仿真通过，内有png仿真图像截屏(verilog description of the practical elimination shake circuit, using three D flip-flop and a JK flip-flop. Prepared source files using the emacs , iverilog simulation adopted, within the simulation images png screenshots)

IRIG_B解码器，直接解码IRIG_B DC(IRIG_B decoder)

对于学习FPGA的同学来说仿真是必不可少的流程 但是仿真的方法signal tap是必须掌握的(For students learning FPGA simulation is an essential process but the simulation method tap signal is a must)

光滑的乘法 ；算法是 ；乘法 ；算法，将两个带符号的二进制数的补码表示法。该算法是由安得烈唐纳德发明的展位 ； ；1950在伯克贝克学院在布卢姆斯伯里研究晶体学，伦敦

AES 128 bit with various device interface on FPGA

基于FPGA的1553b接口设计详细设计论文(1553B design based on FPGA)

浮点加法器的用Verilog实现，32位的浮点加法器(Floating point adder Verilog)

说明：  ADC AD7768-1单通道24bitADC驱动程序(ADC ad7768-1 single channel 24bit ADC driver)

FPGA控制AD逐点采集信号，并将AD转换后的数据串行发送出去。(FPGA to control the signal sampling point by point AD, AD conversion and serial data sent.)

verilog实现计时器timer，可直接用于芯片开发中。(verilog achieve timer, it can be directly used for chip development.)