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DAC_VHDL
DAC VHDL code using SPI method
- 2016-11-09 19:53:01下载
- 积分:1
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tongbu
使用VERILOG开发时钟同步算法,能够从数据信号中提取时钟信息,(Clock synchronization algorithm using VERILOG developed to extract the clock from the data signal information,)
- 2020-11-11 12:39:44下载
- 积分:1
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ytupn
Very suitable for the study using computer vision, Analysis of the signal time domain, frequency domain, cepstrum, cyclic spectrum, etc. The performance of the program has reached a high level.
- 2017-09-02 18:07:13下载
- 积分:1
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ad0809
adc0809 转换,verilog代码(adc0809 conversion, verilog code)
- 2020-12-21 11:09:08下载
- 积分:1
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liyuanlnx_dynamic_led
FPGA数码管显示秒表实验
三种方法实现:
方法一: 对秒计数,得到(秒显示)0~9,
对(秒显示)计数,得到(分秒显示)0~5,
对(分秒显示)计数,得到(分钟显示)0~5,
注意进位时机
方法二: 对秒计数,得到(秒显示)0~9
对秒计数,得到(分秒显示)0~5
对秒计数,得到(分钟显示)0~5
方法三:
只对秒计数,分别取模
%60得到分钟显示 ************************
余数%10得到分秒显示 (据说)取模运算占资源!!!!(也能接受?好像...)
再剩下的余数为秒显示 ************************(Experiment of Digital Tube Display Stopwatch Based on FPGA
Three ways to achieve)
- 2020-06-22 04:40:02下载
- 积分:1
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15-04-0218-01-004a-ieee802-15-4-mac-overview
THE IMPLENTATION OF THE MAC PROTOCOL USING THE FPGA ALTERA 3
- 2013-04-18 20:04:49下载
- 积分:1
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HDB3_encoder_QuartusPrj
说明: HDB3编码Quartus2 10.0的工程,modelsim仿真,有实物图、仿真图以及源程序,适合做通信原理课程设计的同学参考使用(HDB3 encoding Quartus2 10.0 project, modelsim simulation, there are physical map, simulation diagrams and source code, suitable for students of communication theory courses designed for reference use)
- 2011-03-25 08:35:32下载
- 积分:1
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clk
sin波形发生图形,应用智能老师款到即发了快速打击 (sin waveform generation graphics application smart teacher paragraph to that made a rapid strike)
- 2013-02-24 15:46:58下载
- 积分:1
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nios ii系统中Nichestack协议栈的使用
1、工程文件解读
本例程需要的工程文件有以下几种,下面对其意义及作用做了说明:
请点击左侧文件开始预览 !预览只提供20%的代码片段,完整代码需下载后查看 加载中 侵权举报
- 2022-07-05 10:46:12下载
- 积分:1
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fft1024 verilog代码
fft1024 verilog 代码 可以编译成功 建议下载学习(The fft1024 verilog code can compile successful Suggestions for download learning)
- 2017-07-20 10:31:05下载
- 积分:1