verilog经典设计实例

QPSK调制的载波频偏估计，是一个可以调用的函数。接收端进行了一系列的处理。经典的Kay法(QPSK-carrier frequence offset estimation_ kay )

Pipeline processor verilog components

基于FPGA的ip核FIR低通滤波器，实现滤波功能，简单好用(FPGA-based ip core FIR filter for filtering function, easy to use)

实现FPGA多字节的稳定串口通信，改编自特权同学的FPGA代码(Realize the stable serial communication of multi-byte FPGA and adapt the FPGA code from Quan via Quartus by Verilog)

vhdl code for carry lookahead addder

this a example for the LCD for altera FPGA cyclone ii EP2C8. implemented in verilog. tested using altera EP2C8 fpga

VHDL同步串口发送部分，基于Xilinx ISE的编程平台(synchronous serial port sending part on VHDL)

这是个双端口双端口ram的定义，当然读者在此基础上还可以扩充(This is a dual-port dual-port ram definition, of course, on the basis of the readers can also be expanded)

A Full adder using half adder unit in vhdl

Verilog投币式手机充电仪 清华大学数字电子技术基础课程EDA大作业。刚上电数码管全灭，按开始键后，数码管显示全为0。输入一定数额，数码管显示该数额的两倍对应的时间，按确认后开始倒计时。输入数额最多为20。若10秒没有按键，数码管全灭。(Verilog coin operated cell phone charger EDA major homework of digital electronic technology foundation course, Tsinghua University. Just put on the digital tube completely extinguished, press the start button, the digital tube display is 0. Enter a certain amount, the digital tube shows the amount of double the corresponding time, according to the confirmation began countdown. The maximum amount of input is 20. If there is no button in 10 seconds, the digital tube will die out.)