直方图均衡化fpga实现

8b10b编解码，用于光通信和千兆以太网，verilog编写，已验证(8b10b codec for optical communications and Gigabit Ethernet, verilog prepared Verified)

Quartus环境下多路选择器的编写代码，适合初学数字逻辑设计的进行学习(MUX in Quartus)

用verilog实现ldpc最小和译码算法(This code is for the decode of MS-algorithm based on LDPC.)

PI控制器的算法及源码，迅速掌握FPGA的VHDL算法实现！(Algorithm and source code of PI controller, quickly grasp the implementation of VHDL algorithm in FPGA!)

FPGA Verilog HDL 读写SRAM(SRAM FPGA Verilog HDL to read and write)

用verilog语言编写，一个8-bit ALU，可以完成按字节的+、-和与、或、非操作(Using Verilog language, an 8-bit ALU, to be completed by byte+,- And, or, non-operating)

采用Xilinx公司的Spartan6 FPGA设计PCI Express的详细参考资料(Xilinx' s PCI Express, Spartan6 FPGA design, detailed reference information)

2016年4月19日22:51:52 反应测试系统

QUARTUSII 9.0 下的三级流水线中值滤波工程，vhdl源程序等。可用于fpga做图像预处理。(the three stage pipeline median filter project under QUARTUSII 9 , VHDL source program. which can be used by FPGA to do image preprocessing. )

Altera DE2 开发板试验2 第1部分VHDL答案(Altera DE2 Lab2 part1 VHDL answer)