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awb
自动白平衡的verilog实现
通过逻辑实现了白平衡算法(awb design awb design awb design awb design awb design )
- 2012-09-04 13:09:50下载
- 积分:1
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8位大小比较器的VHDL源代码,Magnitude Comparator
VHDL description of a 4...
8位大小比较器的VHDL源代码,Magnitude Comparator
VHDL description of a 4-bit magnitude comparator with expansion inputs-eight compared with the size of the VHDL source code, Magnitude Comparator VHDL description of a 4-bit magnitude comparator inputs with expansion
- 2023-07-28 13:55:03下载
- 积分:1
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在nexys2数字cronometer
该项目是用VHDL编写的,并在Nexys2板套件的4个七段显示器中显示一个测微计的秒、分和小时。时间可以在开关0中停止,在按钮0中复位。显示方式与显示方式不同最小:分段到hr:min通过切换开关1
- 2022-11-12 07:55:03下载
- 积分:1
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基于VHDL开发的自动售货机系统,可实现自动售货过程中的基本功能,具有一定的代表性。...
基于VHDL开发的自动售货机系统,可实现自动售货过程中的基本功能,具有一定的代表性。-VHDL-based development of a vending machine system which can automatically process the basic functions of sales, with a certain representativeness.
- 2022-03-24 04:11:41下载
- 积分:1
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digital-system-design
基于VHDL语言的七段显示管程序, 实现9个数字循环 并且能控制播放速度(SEVEN SEGMENT DISPLAY)
- 2011-02-14 21:02:38下载
- 积分:1
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shape
基于FPGA的成型滤波器的代码,里面内附激励文件,使用verilog编写(FPGA-based shaping filter code, which included incentives files using verilog write)
- 2014-06-05 16:52:06下载
- 积分:1
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数字时中(VHDL)
数字时中(VHDL)-Numbers in (VHDL)! ! ! ! ! ! ! ! ! ! ! ! ! ! ! !
- 2022-03-14 04:30:43下载
- 积分:1
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vhdl经典源代码――vga控制,入门者必须掌握
vhdl经典源代码――vga控制,入门者必须掌握-vhdl classical source code-- vga control, beginners must master
- 2022-03-28 12:21:35下载
- 积分:1
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DVI_LED
基于DVI协议动态全彩LED大屏幕发送卡设计与实现,成本比较低,效果很好,可以实现高清视频(Dynamic full-color LED large screen based on the DVI protocol send a card design and relatively low cost, good effect, and can achieve high-definition video)
- 2012-08-03 13:08:44下载
- 积分:1
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拥有VGA彩色信号发生器Verilog ISE环境
自己编的VGA彩条信号发生器verilog ise环境-Own the VGA color signal generator verilog ise Environment
- 2023-01-14 23:05:03下载
- 积分:1