基于BASYS2模60计数器

基于Montgoery 算法的RSA,FPGA verilog 实现，有测试文件(Based on Montgoery algorithm for RSA,FPGA verilog implementation，bench file)

实现米粒状态机 用verilog语言实现状态机的过程(Implement a state machine with a grain of rice verilog state machine language course)

ALTERA FPGA CLPD

This verilog vga test circuit

ps2键盘输入， RS232串口输出键值（已验证）

基于stm32开发平台的，模拟ad采样程序设计，可直接下载使用(stm32 zhijiexiazaishiyong)

说明：  Matlab - to hdl code for square root

Programmable IIR Filter written in Verilog and its respective modules.

说明：  在FPGA板卡上面，通过单个按键实现串口的发送功能，带仿真需要自行修改一下工程配置(On the FPGA board, the sending function of the serial port is realized by a single key, and the engineering configuration needs to be modified by the simulation)

基于FPGA的键盘PS第二类编码方式的verilog解码程序。基于FPGA的键盘PS第二类编码方式的verilog解码程序。(FPGA keyboard PS encoding the verilog decoding procedures. FPGA keyboard PS encoding the verilog decoding procedures.)