温度补偿的bp神经网络实现

说明：  Use of Kalman and EKF on two-phase permanent magnet synchronous motor of the state estimate CDCDCDCDCCC

VIVADO pl端文档 基于zynq 7020(vivado soc pl example text of zynq)

D-flip flop vhdl implement code

This is a simple verilog code for stopwatch undre xlinx ISE webpack based for NEXYS3 board.

qspi接口控制，指令包括spi、dual spi、quad spi，通过验证，供参考(Qspi interface control, including spi, dual spi, quad spi, for reference.)

verilog编程语言的讲解，有电子科技大学出版(verilog programming language to explain, there is the University of Electronic Science and Technology Publishing)

verilog 代码实现串并转换，有延迟(Verilog code and string conversion, delay)

说明：  多路信号复用基带系统的建模与设计,按位同步复接并掌握四路同步复接器的VHDL设计及系统的时序仿真。(library ieee use ieee.std_logic_1164.all use ieee.std_logic_unsigned.all )

DSP28335与FPGA通过spi通信，此程序为28335为主接收程序(DSP28335 and FPGA through the SPI communication, this procedure for the 28335 receiving procedures)

能够在EDA环境下实现四位十进制数字密码锁的设置与开锁功能，并能更改使用密码，还可以防止抖动(EDA environment to achieve four decimal code lock and unlock function of the settings and change the use of passwords, but also to prevent the jitter)