aynchronous fifo 项目

说明：  用verilog状态机实现简单的自动售货机(Using Verilog state machine to realize simple vending machine)

这包括 verilog 代码为 4 位纹波计数器，编码在 Xilinx ISE 平台上。代码是经过测试，是好的。

包含大量nios开发源码，包含详细的实验步骤和verilog代码，以及怎样用quartus和nios联合开发soc系统，

Design approach for VHDL and FPGA Implementation of Automotive Black Box using CAN Protocol

资源描述 本设计中可以实现测量周期，测量方波的占空比，被测范围1Hz-100MHz。相对误差小于0.001%. 可以测方波、正弦波等波型。同时还有上下左右按键控制显示

低密度校验码 ，很好用的代码，功能已经实现编码和译码(fpga ldpc)

程序是自己编写的，程序的主要功能是实现VGA显示。显示画面为“生日快乐”，并且显示有蛋糕图形。生日快乐四个字可在屏幕上进行流动显示。

完整的TPC编译码VHDL程序，直接就可以运行(TPC encoder and decoder)

时间同步后即可确定每帧数据的起始位置，这样就能完整的截取下每一帧。但是，数据中还带有频偏信息。在常规的通信系统中，多普勒很小仅仅会带来很小的频偏，但是在大多普勒的情况下，频偏将非常大，20马赫的速度将会带来将近34K的频偏。因此，如何很好的纠正频偏即为本系统的难点。 OFDM中，我们将大于子载波间隔倍数的频偏称为整数倍频偏，而将小于一个子载波间隔的频偏称为小数倍频偏。频偏矫正精度只要能保证小于十分之一倍的子载波间隔，频偏就不会对均衡和解调造成影响。本文中我们借鉴这种思想，由于硬件资源限制，我们将在接收端做64点FFT，即相当于将频域划分为64份，我们将小于 的频偏称为小数倍频偏，将 整数倍的频偏称为整数倍频偏。本程序即基于SCHIMDL经典方法完成小数倍频偏纠正(After time synchronization can determine the starting position of each frame data, so you can complete the interception of each frame. However, in the data with frequency information. In conventional communication systems, doppler small will bring only small deviation, but in the case of most of the doppler, frequency PianJiang is very large, 20 Mach speed will lead to deviation of nearly 34 k. Therefore, how to good to correct deviation is the difficulty of this system. OFDM, we will be bigger than the sub-carrier spacing ratio of frequency deviation is called the integer frequency offset, and the interval will be less than a child carrier frequency offset is called decimal frequency doubling. Deviation is less than one over ten times as long as can guarantee accuracy of sub-carrier spacing, deviation will not affect balance and demodulation. This article, we draw lessons from the idea, due to the limited hardware resources, we will do 64 points FFT at the receiving end, which is equ)

说明：  vcs中文使用教程，帮助你快速入门Linux下的VCS操作(VCs Chinese tutorial to help you get started with VCs operation under Linux)