实现

UVM 1.2 golden code, (code for UVM, )

FPGA设计攻略及流程，包含时序收敛和引脚约束(FPGA design strategy and process, including time series convergence and pin constraints)

掌握SDRAM数据读写、刷新、初始化以及FPGA串口收发时序，熟练FIFO IP核的生成和调用。(Master SDRAM data read and write, refresh, initialization and the timing of sending and receiving of the serial port of the FPGA, skilled in the generation and invocation of the FIFO IP core.)

在这里，我们目前使用 VHDL 的 8 位 crc 设计。循环冗余校验是讨论检测错误的通信，使用 vhdl 语言这一过程变得快速和可靠。

Design FPGA in Labview

UART模块的VHDL语言设计(Design of VHDL language based on UART module)

基于System Generator的图像处理工程,多媒体处理FPGA实现的源码,图像增强处理,平滑,锐化,滤波(System Generator based image processing engineering, multimedia processing FPGA implementation source code, image enhancement, smoothing, sharpening, filtering)

针对串行存储器M25P80应用的verilog程序-M25P80 serial memory for applications Verilog program

its the vhdl stuff for ddr sdram controller nice one easily understandable

AMBA总线apb总线的verilog代码以及相关的中断控制。(AMBA bus apb bus verilog code and associated interrupt control.)