UART Verilog sorce 代码和仿真代码和 FIFO 代码

黑金的adda模块资料，质量不错，做电路板的可以作为参考(Black gold ADDA module data)

说明：  FPGA Verilog浮点数乘法运算，采用单精度浮点型小数格式，运算结果精度可设置，可封装成IP核(FPGA Verilog floating-point multi operation, using single precision floating-point decimal format, the accuracy of the operation results can be set, can be packaged into IP core)

基于VHDL的数字计时器，手动可控正计时和倒计时(含复位键和使能键)(VHDL-based digital timer and countdown timer being controlled manually (with the reset button and enable key))

OPSK调制解调。代码思路很清晰，也很干净(Modulation demodulation OPSK. The code ideas very clear, and very clean)

FPGA实现乒乓球游戏 代码及仿真 VGA实现(FPGA realizes table tennis game code and simulation VGA implementation)

简单的Verilog程序，针对音频实验板的AD到DA调通试验，下载执行前请按照自己试验环境更改设置(Simple Verilog program for test the AD to DA loop of universal audio test platform. Please configure it according to the test environment before download and implement the program to FPGA)

说明：  用VERILOG实现的，hdb3编码器和解码器，经过前仿真和后仿真成功(Achieved with the VERILOG, hdb3 encoder and decoder, after a successful pre-simulation and post simulation)

ARM+FPGA JTAG(二合一)原理图与PCB(ARM+ FPGA JTAG (combined) schematic and PCB )

文件名：lcd1602lib.h 内　容：1602液晶的控制端口、数据端口和相关操作(The file name: lcd1602lib. H * inside let: 1602 LCD control port, data port and related operations )

说明：  HDB3编码通过verilog实现，通过modelsim仿真(HDB3 coding is implemented by Verilog and simulated by Modelsim)