七人表决器

Mentor Graphics ModelSim User s Guide Software v6.3g

FPGA控制SRAM读写时序源码，代码桂发，新手一看就懂(FPGA control SRAM write timing source code Guifa novice understand at a glance)

说明：  32位/33M 从模式(target)PCI接口参考设计，Lattice提供。由于PCI时序较复杂，此设计仅能供参考(32/route from the model (target) PCI reference design, Lattice provided. Because PCI timing more complicated, and the design for reference only)

上传的是基于Xilinx的新出的开发板Zedboard的一个简单的知道文档，希望对有关同学有所帮助。(Uploaded a simple know the document based on Xilinx' s new development board Zedboard the hope that some of the students to help.)

通过总结当前对处理器架构的安全性能的处理方法，提出一种增强DSP处理器安全性能的方法。主要从并行性方面进行了改进。最后对改进的方法进行了仿真和结果分析。(By summing up the current security architecture of the processor performance approach, a DSP processor to enhance the safety performance of the method. Mainly from the aspects of parallelism to improve. Finally, improved methods and results of simulation analysis.)

AHBtoAPB设计基于AMBA总线协议的APB Bridge设计(AHB to APB designThe AHB to APB bridge interface is an AHB slave. When accessed (in normal operation or system test) it initiates an access to the APB.)

此代码在FPGA使用VHDL了FFT的基本思想。

一种学习用的小程序，主要用与VHDL仿真的全加器的一段代码！大家可以下载进行修改于仿写-A learning to use a small program, mainly used with the VHDL simulation of a full-adder code! You can download the modified Yu Fang Xie

用fpga制作一个音乐播放器，此为浙江大学信电系fpga教程大实验成果。(Use fpga make a music player, this is the letter Electrical Zhejiang University fpga tutorial big experiment results.)

利用FPGA串口通信向上位机发送数据，使用RS232通信协议，向上位机发送8位数据，其中8八个数据位包括4个信息位，经过7-4汉明编码变为7个信息位，而最低位补0，发送的8位数据为2个16进制数，其2个16进制数通过数码管显示。