七人表决器

Oregano Systems 8051 ip核-Oregano Systems 8051 ip core

异步FIFO的设计 包括testbench 已调试成功-Asynchronous FIFO design includes testbench debug success has been

使用vhdl语言编写的100个常用程序的例子-The use of VHDL language 100 examples of commonly used procedures

用VHDL硬件语言实现的iic顶层控制程序-Using VHDL hardware language to achieve the top level of the IIC control procedures

交通灯通过数码管显示，几种模式可调，还可以时间可设，适合初学者入门参考学习。(LED traffic lights can be set to several modes adjustable time beginners reference ~ ~ ~)

实现mimo-ofdm系统的交织功能，可供参考(Implement the mixed function of mimo- ofdm system, available for reference)

RS译码的Euclid算法及其FPGA实现，并通过仿真器的出结果，对于设计ＲＳ译码很有帮助-RS decoding Euclid algorithm and its FPGA implementation, and through the simulator results are helpful for the design of RS decoder

basic verilog for students

一个开源mips处理器verilog 源码(wishbone interface wishbone interface)

温度码到二进制吗的转换的ｖｅｒｉｌｏｇＨＤＬ代码。-Temperature code to do the conversion of binary code verilogHDL.