编码器程序

VHDL上百实例 包括 ADDER LATCH FIPPER AND ETC..(VHDL hundreds of examples, including ADDER LATCH FIPPER AND ETC ..)

本设计是设计了一个4位全加器的内容，是由4个一位全加器串联而成的(The design is to design a full adder 4 content, is one of four full adder in series from the)

Multi-Digital Down Converter design.

基本逻辑门电路的设计方法，或门的VHDL的设计让你更容易步入VHDL的设计氛围中，简单的或门编制-Basic logic gate circuit design methods, or the door of the VHDL design allows you to more easily into the VHDL design environment, the simple OR gate preparation

用Actel公司的Fusion系列FPGA开发的LCD实验程序-Fusion with Actel s FPGA development series LCD Experimental procedures

使用Verilog编写的时间同步模块，解决位同步问题，ISE12.2下编译通过(Time synchronization module written in Verilog, bit synchronization issues under ISE12.2 compiled by)

硬件描述语言VHDL的频率计程序,可用于做实验,或者初学者借鉴.-Hardware Description Language VHDL of the frequency counter program can be used for experiments, or the beginners learn.

zc706板子原理图，在使用板子时候可以参照设计，使用帮助巨大。(Zc706 board schematic diagram, when using the board can be reference to design, use the help.)

crc32编码的代码(CRC32 coding code)

identify在线调试手册,主要讲了FPGA怎样在线调试文档(identity actel edition tool set release notes)