登录
首页 » VHDL » 编码器程序

编码器程序

于 2022-01-25 发布 文件大小:105.04 kB
0 187
下载积分: 2 下载次数: 1

代码说明:

用于编码器计数,速度能够达到5ms/1圈,速度很快,而且杂波也很好,能够准确应用。已应用在工程中很多年

下载说明:请别用迅雷下载,失败请重下,重下不扣分!

发表评论

0 个回复

  • cycloneII ep2c5 ep2c8
    cycloneII ep2c5 ep2c8
    2022-06-26 08:54:36下载
    积分:1
  • 6_42
    An FPGA Implementation of a HoG-based Object Detection Processor
    2016-04-07 23:42:05下载
    积分:1
  • VHDL_freerisc8
    说明:  一个8位RiSC单片机的VHDL代码, 具有很好的参考价值。(an eight RiSC SCM VHDL code, is a good reference value.)
    2006-02-15 10:58:14下载
    积分:1
  • altera嵌入式设计大赛文章,车载cots设计实现
    altera嵌入式设计大赛文章,车载cots设计实现-Embedded Design Contest altera article, cots Car Design
    2022-05-20 14:21:28下载
    积分:1
  • AD9777_SPI_CONFIG
    verilog ad9777 ad芯片的配置程序,SPI接口协议 16bit DA(Verilog ad9777 AD chip configuration program, SPI interface protocols for 16 bit DA)
    2020-07-29 21:08:38下载
    积分:1
  • 本项目是基于SR和D触发器的使用vhdl.this是100正确的内容。
    this project is based on sr and d flip flop using vhdl.this is the 100 correct code,reference is taken from book digital electrionics written by anand kumar.please use quatrus to access this code.this code can be used for the final year project for engineering. Here dataflow techniques and behavioural -this project is based on sr and d flip flop using vhdl.this is the 100 correct code,reference is taken from book digital electrionics written by anand kumar.please use quatrus to access this code.this code can be used for the final year project for engineering. Here dataflow techniques and behavioural
    2022-06-27 01:31:46下载
    积分:1
  • fault
    fault minimization using genetic algorithm
    2013-11-19 20:05:06下载
    积分:1
  • zuse
    验证阻塞赋值与非阻塞的赋值赋值过程的先后顺序(Verification of the order of assignment and non blocking assignment)
    2017-12-18 17:04:23下载
    积分:1
  • password
    verilog代码实现的数字密码锁。通过4个并行的10位移位寄存器,分别记录在时钟上升沿时A,B,C,D的输入情况,比如某上升沿输入A,相应时刻A对应的移位寄存器输入1,其他三个移位寄存器输入都为0.另外4个并行的10位寄存器记录密码。这样,密码锁不仅可以识别字符数量,还可以判断出字符的输入次序。(verilog code of digital lock. By four parallel 10-bit shift register, respectively, recorded in the clock rising edge A, B, C, D of inputs, such as a rising edge of input A, the corresponding moments A 1 corresponding to the input shift register, the other three shift bit register inputs are 0. another four parallel 10-bit registers record the password. This lock can not only identify the number of characters, you can also determine the character of the input sequence.)
    2011-10-18 21:45:45下载
    积分:1
  • 3Verilog语言要素
    说明:  Verilog学习文档,介绍基本知识点,语言要素(for learning Verilog)
    2020-03-24 10:01:15下载
    积分:1
  • 696516资源总数
  • 106914会员总数
  • 0今日下载